Section 21 Electrical Characteristics
Item
SCI
Input
Asyn-
clock
chronous
cycle
Syn-
chronous
Input clock rise
time
Input clock fall
time
Input clock
pulse width
Transmit data
delay time
Receive data
setup time
(synchronous)
Receive
Clock
data hold
input
time (syn-
Clock
chronous)
output
DMAC TEND delay
time 1
TEND delay
time 2
DREQ setup
time
DREQ hold
time
Rev. 4.00 Jan 26, 2006 page 712 of 938
REJ09B0276-0400
A
Symbol Min
Max
t
4
—
Scyc
6
—
t
1.5
—
SCKr
t
1.5
—
SCKf
t
0.4
0.6
SCKW
t
—
100
TXD
t
100
—
RXS
t
100
—
RXH
0
—
t
—
100
TED1
t
—
100
TED2
t
40
—
DRQS
t
10
—
DRQH
Condition
B
C
Min
Max
Min
Max
4
—
4
—
6
—
6
—
1.5
—
1.5
—
1.5
—
1.5
—
0.4
0.6
0.4
0.6
—
100
—
100
100
—
100
—
100
—
100
—
0
—
0
—
—
100
—
50
—
100
—
50
40
—
25
—
10
—
10
—
Test
Unit
Conditions
t
Figure 21.23
cyc
t
cyc
t
cyc
t
cyc
t
Scyc
ns
Figure 21.24
ns
ns
ns
ns
Figure 21.25,
figure 21.26
ns
ns
Figure 21.27
ns