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Section 8 I/O Ports
8.11.2
Register Descriptions
Table 8.18 summarizes the registers of port A.
Table 8.18 Port A Registers
Address*
Name
H'EE009
Port A data direction
register
H'FFFD9
Port A data register
Note: * Lower 20 bits of the address in advanced mode.
Port A Data Direction Register (PADDR): PADDR is an 8-bit write-only register that can select
input or output for each pin in port A. When pins are used for TPC output, the corresponding
PADDR bits must also be set.
Bit
PA DDR
Initial value
Modes
3, 4
Read/Write
Modes
Initial value
1, 2, 5,
Read/Write
6 and 7
The pin functions that can be selected for pins PA
modes 3 to 5. For the method of selecting the pin functions, see tables 8.19 and 8.20.
The pin functions that can be selected for pins PA
method of selecting the pin functions, see table 8.21.
When port A functions as an input/output port, a pin in port A becomes an output port if the
corresponding PADDR bit is set to 1, and an input port if this bit is cleared to 0. In modes 3 and 4,
PA
DDR is fixed at 1 and PA
7
PADDR is a write-only register. Its value cannot be read. All bits return 1 when read.
Rev. 4.00 Jan 26, 2006 page 308 of 938
REJ09B0276-0400
PADDR
PADR
7
6
5
PA DDR
PA DDR
7
6
5
1
0
0
—
W
W
0
0
0
W
W
W
functions as the A
7
Initial Value
R/W
Modes 1, 2, 5, 6 and 7
W
H'00
R/W
H'00
4
3
PA DDR
PA DDR
4
3
0
0
W
W
0
0
W
W
Port A data direction 7 to 0
These bits select input or output for port A pins
to PA
differ between modes 1, 2, 6, and 7, and
7
4
to PA
are the same in modes 1 to 7. For the
3
0
address output pin.
20
Modes 3, 4
H'80
H'00
2
1
PA DDR
PA DDR
PA DDR
2
1
0
0
W
W
0
0
W
W
0
0
0
W
0
W
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