Renesas H8/3067 Series User Manual page 850

Appendix B Internal I/O Registers
DTCR0B—Data Transfer Control Register 0B (cont)
•
Full address mode
7
Bit
DTME
Initial value 0
Read/Write R/W R/W
Data transfer master enable
0
Data transfer is disabled
1
Data transfer is enabled
Destination address increment/decrement (bit 5)
Destination address increment/decrement enable (bit 4)
Bit 5 Bit 4
DAID DAIDE
0
0
1
0
1
1
Rev. 4.00 Jan 26, 2006 page 826 of 938
REJ09B0276-0400
6 5 4

DAID DAIDE
0 0 0
R/W R/W
Increment/Decrement Enable
MARB is held fixed
Incremented: If DTSZ = 0, MARB is incremented by 1 after each transfer
If DTSZ = 1, MARB is incremented by 2 after each transfer
MARB is held fixed
Decremented: If DTSZ = 0, MARB is decremented by 1 after each transfer
If DTSZ = 1, MARB is decremented by 2 after each transfer
H'FFF2F
3 2 1
TMS DTS2B DTS1B
0 0 0
R/W R/W R/W
Data transfer select 2B to 0B
Bit 2 Bit 1 Bit 0
DTS2B DTS1B DTS0B
Auto-request
0
(burst mode)
0
Not available
1
0
Auto-request
0
1
(cycle-steal mode)
Not available
1
0
Not available
0
1
Not available
1
Falling edge input of
0
DREQ
1
Low level input at DREQ
1
Transfer mode select
0
Destination is the block area in block transfer mode
1
Source is the block area in block transfer mode
DMAC0
0
DTS0B
0
R/W
Data Transfer Activation Source
Normal Mode Block Transfer Mode
Compare match/input
capture A interrupt from
16-bit timer channel 0
Compare match/input
capture A interrupt from
16-bit timer channel 1
Compare match/input
capture A interrupt from
16-bit timer channel 2
A/D converter conversion
end interrupt
Not available
Not available
Falling edge input of
DREQ
Not available