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RAM Control Register
Bit
Modes
Initial value
1 to 4
R/W
Modes
Initial value
5 to 7
R/W
RAM select, RAM2, RAM1
Note: * In mode 6 (single-chip normal mode), flash memory emulation by RAM is not
Note: This register is used only in the flash memory and flash memory R versions.
Reading the corresponding address in a mask ROM version will always return
1s, and writes to this address are disabled.
RAMCR
7
6
—
1
1
1
1
Reserved bits
Bit 3
Bit 2
Bit 1
RAMS RAM2 RAM1
0
0/1
0/1
1
0
0
1
1
0
1
supported; these bits can be modified, but must not be set to 1.
Appendix B Internal I/O Registers
H'EE077
5
4
3
—
—
RAMS
1
1
0
R
1
1
0
R/W*
RAM Area
H'FFF000 to H'FFF3FF
H'000000 to H'0003FF
H'000400 to H'0007FF
H'000800 to H'000BFF
H'000C00 to H'000FFF
Rev. 4.00 Jan 26, 2006 page 815 of 938
Flash Memory
2
1
0
RAM2
RAM1
—
0
0
1
R
R
0
0
1
R/W*
R/W*
RAM Emulation Status
No emulation
Mapping RAM
REJ09B0276-0400
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