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Section 9 16-Bit Timer
2. For periodic counting, set CCLR1 and CCLR0 in TCR to have TCNT cleared at GRA compare
match or GRB compare match.
3. Set TIOR to select the output compare function of GRA or GRB, whichever was selected in
step 2.
4. Write the count period in GRA or GRB, whichever was selected in step 2.
5. Set the STR bit to 1 in TSTR to start the timer counter.
• Free-running and periodic counter operation
A reset leaves the counters (TCNTs) in 16-bit timer channels 0 to 2 all set as free-running
counters. A free-running counter starts counting up when the corresponding bit in TSTR is set
to 1. When the count overflows from H'FFFF to H'0000, the OVF flag is set to 1 in TISRC.
After the overflow, the counter continues counting up from H'0000. Figure 9.13 illustrates
free-running counting.
TCNT value
H'FFFF
H'0000
STR0 to
STR2 bit
OVF
When a channel is set to have its counter cleared by compare match, in that channel TCNT
operates as a periodic counter. Select the output compare function of GRA or GRB, set bit CCLR1
or CCLR0 in TCR to have the counter cleared by compare match, and set the count period in GRA
or GRB. After these settings, the counter starts counting up as a periodic counter when the
corresponding bit is set to 1 in TSTR. When the count matches GRA or GRB, the IMFA or IMFB
flag is set to 1 in TISRA/TISRB and the counter is cleared to H'0000. If the corresponding IMIEA
or IMIEB bit is set to 1 in TISRA/TISRB, a CPU interrupt is requested at this time. After the
compare match, TCNT continues counting up from H'0000. Figure 9.14 illustrates periodic
counting.
Rev. 4.00 Jan 26, 2006 page 364 of 938
REJ09B0276-0400
Figure 9.13 Free-Running Counter Operation
Time
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