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Figure 7.8 illustrates how normal mode operates.
Address T
A
Address B
A
Legend
L
= initial setting of MARA
A
L
= initial setting of MARB
B
N
= initial setting of ETCRA
T
= L
A
A
= L + SAIDE • (−1)
B
A
A
T
= L
B
B
= L + DAIDE • (−1)
B
B
B
Transfers can be requested (activated) by an external request or auto-request. An auto-requested
transfer is activated by the register settings alone. The designated number of transfers are executed
automatically. Either cycle-steal or burst mode can be selected. In cycle-steal mode the DMAC
releases the bus temporarily after each transfer. In burst mode the DMAC keeps the bus until the
transfers are completed, unless there is a bus request from a higher-priority bus master.
Transfer
• (2
• N − 1)
SAID
DTSZ
• (2
• N − 1)
DAID
DTSZ
Figure 7.8 Operation in Normal Mode
Section 7 DMA Controller
Rev. 4.00 Jan 26, 2006 page 241 of 938
Address T
B
Address B
B
REJ09B0276-0400
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