Renesas H8/3067 Series User Manual page 182

Renesas 16-bit single-chip microcomputer
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Section 6 Bus Controller
16-Bit, Three-State-Access Areas
Figures 6.11 to 6.13 show the timing of bus control signals for a 16-bit, three-state-access area. In
these areas, the upper data bus (D
bus (D
to D
) in accesses to odd addresses. Wait states can be inserted.
7
0
Address bus
Read access
Write access
Note: n = 7 to 0
Figure 6.11 Bus Control Signal Timing for 16-Bit, Three-State-Access Area (1)
Rev. 4.00 Jan 26, 2006 page 158 of 938
REJ09B0276-0400
to D
) is used in accesses to even addresses and the lower data
15
8
T
φ
CSn
AS
RD
D
to D
15
8
D
to D
7
0
HWR
LWR
High
D
to D
15
8
D
to D
7
0
(Byte Access to Even Address)
Bus cycle
T
1
2
Even external address in area n
Valid
Undetermined data
T
3
Valid
Invalid

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