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8.12.2
Register Descriptions
Table 8.22 summarizes the registers of port B.
Table 8.22 Port B Registers
Address*
Name
H'EE00A
Port B data direction register
H'FFFDA
Port B data register
Note: * Lower 20 bits of the address in advanced mode.
Port B Data Direction Register (PBDDR): PBDDR is an 8-bit write-only register that can select
input or output for each pin in port B. When pins are used for TPC output, the corresponding
PBDDR bits must also be set.
Bit
7
PB DDR
7
Initial value
0
Read/Write
W
The pin functions that can be selected for port B differ between modes 1 to 5, and modes 6 and 7.
For the method of selecting the pin functions, see tables 8.23 and 8.24.
When port B functions as an input/output port, a pin in port B becomes an output port if the
corresponding PBDDR bit is set to 1, and an input port if this bit is cleared to 0.
PBDDR is a write-only register. Its value cannot be read. All bits return 1 when read.
PBDDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode
it retains its previous setting. Therefore, if a transition is made to software standby mode while
port B is functioning as an input/output port and a PBDDR bit is set to 1, the corresponding pin
maintains its output state.
6
5
PB DDR
PB DDR
PB DDR
6
5
0
0
W
W
Port B data direction 7 to 0
These bits select input or output for port B pins
Abbreviation
R/W
PBDDR
W
PBDR
R/W
4
3
2
PB DDR
PB DDR
4
3
2
0
0
0
W
W
W
Rev. 4.00 Jan 26, 2006 page 319 of 938
Section 8 I/O Ports
Initial Value
H'00
H'00
1
0
PB DDR
PB DDR
1
0
0
0
W
W
REJ09B0276-0400
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