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The transfer count is specified as a 16-bit value in ETCR. The ETCR value is decremented by 1 at
each transfer. When the ETCR value reaches H'0000, the DTE bit is cleared, the transfer ends, and
a CPU interrupt is requested. The maximum transfer count is 65,536, obtained by setting ETCR to
H'0000.
Transfers can be requested (activated) by compare match/input capture A interrupts from 16-bit
timer channels 0 to 2, transmit-data-empty and receive-data-full interrupts from SCI channel 0,
conversion-end interrupts from the A/D converter, and external request signals.
For the detailed settings see section 7.3.4, Data Transfer Control Registers (DTCR).
Figure 7.5 shows a sample setup procedure for idle mode.
Transfer
1 byte or word is
transferred per request
Figure 7.4 Operation in Idle Mode
Section 7 DMA Controller
Rev. 4.00 Jan 26, 2006 page 235 of 938
IOAR
REJ09B0276-0400
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