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Bit 0—Program (P) *
PSU, EV, PV, or E bit at the same time.
Bit 0:
P
Description
0
Program mode cleared
1
Transition to program mode
[Setting condition]
When FWE = 1, SWE = 1, and PSU = 1
Notes: 1. Do not set two or more bits at the same time.
Do not turn off V
2. Do not set/clear the SWE bit simultaneously with other bits (ESU, PSU, EV, PV, E, P).
3. Set the P and E bits according to the program and erase algorithms shown in section
18.5, Programming and Erasing Flash Memory.
For the usage precautions, see section 18.9, Notes on Flash Memory
Programming/Erasing.
18.3.2
Erase Block Register (EBR)
EBR is an 8-bit register that designates the flash memory block for erasure. EBR is initialized to
H'00 by a reset, in hardware standby mode, or software standby mode, when a high level is not
input to the FWE terminal, or when the FLMCR SWE bit is 0 when a high level is applied to the
FWE terminal. When a bit is set in EBR, the corresponding block can be erased. Other blocks are
erase - protected. The blocks are erased block by block. Therefore, set only one bit in EBR; do not
set bits in EBR to erase two or more blocks at the same time.
Each bit in EBR cannot be set until the SWE bit in FLMCR is set. The flash memory block
configuration is shown in table 18.4. To erase all the blocks, erase each block sequentially.
The H8/3067 Group does not support the on-board programming mode in mode 6, so bits in this
register cannot be set to 1 in mode 6.
Bit
Modes 1
Initial value
to 4, and 6
R/W
Modes 5
Initial value
and 7
R/W
*
1
3
: Selects program mode transition or clearing. Do not set the SWE, ESU,
when a bit is set.
CC
7
6
EB7
EB6
0
0
R
R
0
0
R/W
R/W
5
4
3
EB5
EB4
EB3
0
0
0
R
R
R
0
0
0
R/W
R/W
R/W
Rev. 4.00 Jan 26, 2006 page 615 of 938
Section 18 ROM
(Initial value)
2
1
0
EB2
EB1
EB0
0
0
0
R
R
R
0
0
0
R/W
R/W
R/W
REJ09B0276-0400
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