Renesas H8/3067 Series User Manual page 783

Mnemonic
DIVXU. W Rs, ERd W
DIVXS. B Rs, Rd B
DIVXS. W Rs, ERd W
CMP.B #xx:8, Rd B 2
CMP.B Rs, Rd B
CMP.W #xx:16, Rd W 4
CMP.W Rs, Rd W
CMP.L #xx:32, ERd L 6
CMP.L ERs, ERd L
NEG.B Rd B
NEG.W Rd W
NEG.L ERd L
EXTU.W Rd W
EXTU.L ERd L
EXTS.W Rd W
EXTS.L ERd L
Addressing Mode and
Instruction Length (bytes)
2
4
4
2
2
2
2
2
2
2
2
2
2
Appendix A Instruction Set
Operation I
ERd32 ÷ Rs16 → ERd32   (6) (7)  
(Ed: remainder,
Rd: quotient)
(unsigned division)
Rd16 ÷ Rs8 → Rd16   (8) (7)  
(RdH: remainder,
RdL: quotient)
(signed division)
ERd32 ÷ Rs16 → ERd32   (8) (7)  
(Ed: remainder,
Rd: quotient)
(signed division)

Rd8–#xx:8

Rd8–Rs8
Rd16–#xx:16 — (1)
Rd16–Rs16 — (1)
ERd32–#xx:32 — (2)
ERd32–ERs32 — (2)
0–Rd8 → Rd8 
0–Rd16 → Rd16 
0–ERd32 → ERd32 
0 → (<bits 15 to 8>   0
of Rd16)
0 → (<bits 31 to 16>   0
of ERd32)
(<bit 7> of Rd16) →  
(<bits 15 to 8> of Rd16)
(<bit 15> of ERd32) →  
(<bits 31 to 16> of
ERd32)
Rev. 4.00 Jan 26, 2006 page 759 of 938
No. of
States*
Condition Code
H N Z V C
22
16
24
2
2
4
2
6
2
2
2
2
0 
2
0 
2
0 
2
0 
2
REJ09B0276-0400
1