Module Standby Control Register L (Mstcrl) - Renesas H8/3067 Series User Manual

Section 20 Power-Down State
Bit 1—Module Standby H1 (MSTPH1): Selects whether to place the SCI1 in standby.
Bit 1
MSTPH1 Description
0 SCI1 operates normally
1 SCI1 is in standby state
Bit 0—Module Standby H0 (MSTPH0): Selects whether to place the SCI0 in standby.
Bit 0
MSTPH0 Description
0 SCI0 operates normally
1 SCI0 is in standby state
20.2.3

Module Standby Control Register L (MSTCRL)

MSTCRL is an 8-bit readable/writable register that controls the module standby function, which
places individual on-chip supporting modules in the standby state. Module standby can be
designated for the DMAC, 16-bit timer, DRAM interface, 8-bit timer, and A/D converter modules.
Bit 7
MSTPL7
Initial value 0
Read/Write R/W
MSTCRL is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Rev. 4.00 Jan 26, 2006 page 680 of 938
REJ09B0276-0400
6 5

MSTPL5
0 0
R/W R/W
Reserved bits
4 3
MSTPL4 MSTPL3 MSTPL2
0 0
R/W R/W
Module standby L7, L5 to L2, L0
These bits select modules to be
placed in standby
(Initial value)
(Initial value)
2 1

MSTPL0
0 0
R/W R/W R/W
0
0