Renesas H8/3067 Series User Manual page 557

• Transmitting and Receiving Data Simultaneously (Synchronous Mode): Figure 13.20 shows a
sample flowchart for transmitting and receiving serial data simultaneously and indicates the
procedure to follow.
Initialize
Start of transmitting and receiving
Read TDRE flag in SSR
No
TDRE = 1
Yes
Write transmit data in TDR and
clear TDRE flag to 0 in SSR
Read ORER flag in SSR
ORER = 1
No
Read RDRF flag in SSR
No
RDRF = 1
Yes
Read receive data from RDR, and
clear RDRF flag to 0 in SSR
No
End of transmitting
and receiving?
Yes
Clear TE and RE bits to 0 in SCR
<End>
Note: When switching from transmitting or receiving to simultaneous transmitting and receiving, clear both the TE bit
and the RE bit to 0, then set both bits to 1 simultaneously.
Figure 13.20 Sample Flowchart for Simultaneous Serial Transmitting and Receiving
(1)
SCI initialization: the transmit data output function of the
(1)
TxD pin and the read data input function of the RxD pin
are selected, enabling simultaneous transmitting and
receiving.
(2)
SCI status check and transmit data write: read SSR, check
(2)
that the TDRE flag is 1, then write transmit data in TDR
and clear the TDRE flag to 0.
Notification that the TDRE flag has changed from 0 to 1
can also be given by the TXI interrupt.
(3)
Receive error handling: if a receive error occurs, read the
ORER flag in SSR, then after executing the necessary
error handling, clear the ORER flag to 0.
Neither transmitting nor receiving can resume while the
ORER flag remains set to 1.
(4)
SCI status check and receive data read: read SSR, check
that the RDRF flag is 1, then read receive data from RDR
and clear the RDRF flag to 0. Notification that the RDRF
flag has changed from 0 to 1 can also be given by the RXI
Yes
interrupt.
(3)
(5) To continue transmitting and receiving serial data: check
the RDRF flag, read RDR, and clear the RDRF flag to 0
Error handling
before the MSB (bit 7) of the current frame is received.
Also check that the TDRE flag is set to 1, indicating that
(4)
data can be written, write data in TDR, then clear the
TDRE flag to 0 before the MSB (bit 7) of the current frame
is transmitted. When the DMAC is activated by a transmit-
data-empty interrupt request (TXI) to write data in TDR,
the TDRE flag is checked and cleared automatically.
When the DMAC is activated by a receive-data-full
interrupt request (RXI) to read RDR, the RDRF flag is
cleared automatically.
(5)
Section 13 Serial Communication Interface
Rev. 4.00 Jan 26, 2006 page 533 of 938
REJ09B0276-0400