Breq Pin Input Timing - Renesas H8/3067 Series User Manual

BRCR Write Timing: Data written to BRCR to switch between A
generic input or output takes effect starting from the T
shows the timing when a pin is changed from generic input to A
φ
Address bus
PA to PA
7
( A to A
23

BREQ Pin Input Timing

BREQ BREQ BREQ
6.11.2
After driving the BREQ pin low, hold it low until BACK goes low. If BREQ returns to the high
level before BACK goes lows, the bus arbiter may operate incorrectly.
To terminate the external-bus-released state, hold the BREQ signal high for at least three states. If
BREQ is high for too short an interval, the bus arbiter may operate incorrectly.
4
High-impedance
)
20
Figure 6.51 BRCR Write Timing
state of the BRCR write cycle. Figure 6.51
3
, A
23
T T
1 2
BRCR address
Rev. 4.00 Jan 26, 2006 page 207 of 938
Section 6 Bus Controller
, A , A , or A output and
23 22 21 20
, A , or A output.
22 21 20
T
3
REJ09B0276-0400