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Section 6 Bus Controller
Bits 7 and 6—Multiplex Control 1 and 0 (MXC1, MXC0): These bits select the row
address/column address multiplexing method used on the DRAM interface. In burst operation, the
row address used for comparison is determined by the setting of these bits and the bus width of the
relevant area set in ABWCR.
Bit 7
Bit 6
MXC1
MXC0
Description
0
0
Column address: 8 bits
Compared address:
Modes 1, 2
Modes 3, 4, 5
1
Column address: 9 bits
Compared address:
Modes 1, 2
Modes 3, 4, 5
1
0
Column address: 10 bits
Compared address:
Modes 1, 2
Modes 3, 4, 5
1
Illegal setting
CAS Output Pin Select (CSEL): Selects the UCAS and LCAS output pins when areas 2
CAS
CAS
Bit 5—CAS
to 5 are designated as DRAM space.
Bit 5
CSEL
Description
PB4 and PB5 selected as UCAS and LCAS output pins
0
HWR and LWR selected as UCAS and LCAS output pins
1
Rev. 4.00 Jan 26, 2006 page 138 of 938
REJ09B0276-0400
8-bit access space
16-bit access space
8-bit access space
16-bit access space
8-bit access space
16-bit access space
8-bit access space
16-bit access space
8-bit access space
16-bit access space
8-bit access space
16-bit access space
A
to A
19
8
A
to A
19
9
A
to A
23
8
A
to A
23
9
A
to A
19
9
A
to A
19
10
A
to A
23
9
A
to A
23
10
A
to A
19
10
A
to A
19
11
A
to A
23
10
A
to A
23
11
(Initial value)
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