Renesas H8/3067 Series User Manual page 400

Section 9 16-Bit Timer
Figure 9.28 shows examples of the output of PWM waveforms with duty cycles of 0% and 100%.
If the counter is cleared by compare match with GRB, and GRA is set to a higher value than GRB,
the duty cycle is 0%. If the counter is cleared by compare match with GRA, and GRB is set to a
higher value than GRA, the duty cycle is 100%.
TCNT value
GRB
GRA
H'0000
TIOCA
TCNT value
GRA
GRB
H'0000
TIOCA
Rev. 4.00 Jan 26, 2006 page 376 of 938
REJ09B0276-0400
Counter cleared by compare match B
Write to GRA
a. 0% duty cycle (TOA=0)
Counter cleared by compare match A
Write to GRB
b. 100% duty cycle (TOA=1)
Figure 9.28 PWM Mode (Example 2)
Write to GRA
Write to GRB
Time
Time