Renesas H8/3067 Series User Manual page 702

Section 20 Power-Down State
Bit 7—Software Standby (SSBY): Enables transition to software standby mode. When software
standby mode is exited by an external interrupt, this bit remains set to 1 after the return to normal
operation. To clear this bit, write 0.
Bit 7
SSBY Description
0 SLEEP instruction causes transition to sleep mode
1 SLEEP instruction causes transition to software standby mode
Bits 6 to 4—Standby Timer Select (STS2 to STS0): These bits select the length of time the CPU
and on-chip supporting modules wait for the clock to settle when software standby mode is exited
by an external interrupt. If the clock is generated by a crystal resonator, set these bits according to
the clock frequency so that the waiting time will be at least 7 ms (oscillation settling time). See
table 20.3. If an external clock is used, any setting is permitted.
Bit 6 Bit 5 Bit 4
STS2 STS1 STS0
0 0 0
1
1 0
1
1 0 0
1
1 0
1
Bit 1—Software Standby Output Port Enable (SSOE): Specifies whether the address bus and
bus control signals (CS
outputs or fixed high, or placed in the high-impedance state in software standby mode.
Bit 1
SSOE Description
0 In software standby mode, the address bus and bus control signals
are all high-impedance
1 In software standby mode, the address bus retains its output state
and bus control signals are fixed high
Rev. 4.00 Jan 26, 2006 page 678 of 938
REJ09B0276-0400
Description
Waiting time = 8,192 states
Waiting time = 16,384 states
Waiting time = 32,768 states
Waiting time = 65,536 states
Waiting time = 131,072 states
Waiting time = 262,144 states
Waiting time = 1,024 states
Illegal setting
to CS , AS, RD, HWR, LWR, UCAS, LCAS, and RFSH) are kept as
0 7
(Initial value)
(Initial value)
(Initial value)