Table of Contents
Advertisement
12.4
Interrupts
During interval timer operation, an overflow generates an interval timer interrupt (WOVI). The
interval timer interrupt is requested whenever the OVF bit is set to 1 in TCSR.
12.5
Usage Notes
Contention between TCNT Write and Increment: If a timer counter clock pulse is generated
during the T
state of a write cycle to TCNT, the write takes priority and the timer count is not
3
incremented. See figure 12.8.
φ
TCNT
Internal write
signal
TCNT input
clock
TCNT
Figure 12.8 Contention between TCNT Write and Count up
Changing CKS2 to CKS0 Bit: Halt TCNT by clearing the TME bit to 0 in TCSR before
changing the values of bits CKS2 to CKS0.
CPU: TCNT write cycle
T
T
1
2
N
Section 12 Watchdog Timer
T
3
M
Counter write data
Rev. 4.00 Jan 26, 2006 page 475 of 938
REJ09B0276-0400
Advertisement
Table of Contents
