Renesas H8/3067 Series User Manual page 367

Bit 5—Input Capture/Compare Match Interrupt Enable A1 (IMIEA1): Enables or disables
the interrupt requested by the IMFA1 flag when IMFA1 is set to 1.
Bit 5
IMIEA1 Description
0 IMIA1 interrupt requested by IMFA1 flag is disabled
1 IMIA1 interrupt requested by IMFA1 flag is enabled
Bit 4—Input Capture/Compare Match Interrupt Enable A0 (IMIEA0): Enables or disables
the interrupt requested by the IMFA0 flag when IMFA0 is set to 1.
Bit 4
IMIEA0 Description
0 IMIA0 interrupt requested by IMFA0 flag is disabled
1 IMIA0 interrupt requested by IMFA0 flag is enabled
Bit 3—Reserved: This bit cannot be modified and is always read as 1.
Bit 2—Input Capture/Compare Match Flag A2 (IMFA2): This status flag indicates GRA2
compare match or input capture events.
Bit 2
IMFA2 Description
0 [Clearing conditions]
Read IMFA2 when IMFA2 =1, then write 0 in IMFA2.
DMAC activated by IMIA2 interrupt.
1 [Setting conditions]
TCNT2 = GRA2 when GRA2 functions as an output compare register.
TCNT2 value is transferred to GRA2 by an input capture signal when GRA2 functions as
an input capture register.
Section 9 16-Bit Timer
Rev. 4.00 Jan 26, 2006 page 343 of 938
(Initial value)
(Initial value)
(Initial value)
REJ09B0276-0400