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8.12
Port B
8.12.1
Overview
Port B is an 8-bit input/output port that is also used for output (TP
programmable timing pattern controller (TPC), input/output (TMIO
the 8-bit timer, CS
to CS
7
and output (TxD
, RxD
2
(UCAS, LCAS) by the DRAM interface. See table 8.23 to 8.24 for the selection of pin functions.
A reset or hardware standby transition leaves port B as an input port.
For output of CS
to CS
7
connected to areas 2, 3, 4, and 5, the CS
areas. For details see 6.5, DRAM Interface. Pins not assigned to any of these functions are
available for generic input/output. Figure 8.11 shows the pin configuration of port B.
When DRAM is connected to areas 2, 3, 4, and 5, the CS
pins for these areas. For details see 6.5, DRAM Interface.
Pins in port B can drive one TTL load and a 30-pF capacitive load. They can also drive darlington
transistor pair.
output, input (DREQ
4
, SCK
) by serial communication interface channel 2 (SCI2), and output
2
2
in modes 1 to 5, see section 6.3.4, Chip Select Signals. When DRAM is
4
and CS
4
to TP
15
, TMO
3
, DREQ
) to the DMA controller (DMAC), input
1
0
output pins become RAS output pins for these
5
and CS
output pins become RAS output
4
5
Rev. 4.00 Jan 26, 2006 page 317 of 938
Section 8 I/O Ports
) from the
8
, TMIO
, TMO
) by
2
1
0
REJ09B0276-0400
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