Section 19 Clock Pulse Generator
t
t
EXH
EXL
× 0.7
V
CC
EXTAL
× 0.5
V
CC
0.3 V
t
t
EXr
EXf
Figure 19.6 External Clock Input Timing
V
2.7 V
CC
V
STBY
IH
EXTAL
φ (internal or
external)
RES
t
DEXT
Figure 19.7 External Clock Output Settling Delay Timing
Rev. 4.00 Jan 26, 2006 page 671 of 938
REJ09B0276-0400