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16-Bit, Two-State-Access Areas: Figures 6.14 to 6.16 show the timing of bus control signals for
a 16-bit, two-state-access area. In these areas, the upper data bus (D
even addresses and the lower data bus (D
be inserted.
Read access
Write access
Note: n = 7 to 0
Figure 6.14 Bus Control Signal Timing for 16-Bit, Two-State-Access Area (1)
to D
) in accesses to odd addresses. Wait states cannot
7
0
φ
Address bus
Even external address in area n
CS
n
AS
RD
D
to D
15
8
D
to D
7
0
HWR
LWR
D
to D
15
8
D
to D
7
0
(Byte Access to Even Address)
to D
15
Bus cycle
T
T
1
2
Valid
Invalid
High
Valid
Undetermined data
Rev. 4.00 Jan 26, 2006 page 161 of 938
Section 6 Bus Controller
) is used in accesses to
8
REJ09B0276-0400
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