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Section 6 Bus Controller
Contention between RTCNT Write and Increment: If an increment pulse occurs in the T
state
3
of an RTCNT write cycle, writing takes priority and RTCNT is not incremented. See Figure 6.40.
T
T
T
1
2
3
φ
Address bus
RTCNT address
Internal write signal
RTCNT input clock
RTCNT
N
M
Counter write data
Figure 6.40 Contention between RTCNT Write and Increment
Rev. 4.00 Jan 26, 2006 page 193 of 938
REJ09B0276-0400
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