Renesas H8/3067 Series User Manual page 875

TCR2—Timer Control Register 2
TCR3—Timer Control Register 3
7
Bit
CMIEB
Initial value 0
Read/Write R/W
Compare match interrupt enable B
0
CMIB interrupt requested by CMFB is disabled
1
CMIB interrupt requested by CMFB is enabled
6 5 4
CMIEA OVIE CCLR1
0 0 0
R/W R/W R/W
Counter clear 1 and 0
0
0
1
0
1
1
Timer overflow interrupt enable
0
OVI interrupt requested by OVF is disabled
1
OVI interrupt requested by OVF is enabled
Compare match interrupt enable A
0
CMIA interrupt requested by CMFA is disabled
1
CMIA interrupt requested by CMFA is enabled
Appendix B Internal I/O Registers
H'FFF90
H'FFF91
3 2 1
CCLR0 CKS2 CKS1
0 0 0
R/W R/W R/W
Clock select 2 to 0
CSK2 CSK1 CSK0
0 Clock input is disabled
0
Internal clock, counted on rising edge
1
of φ/8
Internal clock, counted on rising edge
0
of φ/64
1
0
Internal clock, counted on rising edge
1
of φ/8192
Channel 2:
Count on TCNT3 overflow signal*
0
Channel 3:
0
Count on TCNT2 compare match A*
1
1
External clock, counted on falling edge
0
External clock, counted on rising edge
1
External clock, counted on both
1
rising and falling edges
Note: * If the clock input of channel 2 is the TCNT3 overflow
signal and that of channel 3 is the TCNT2 compare
match signal, no incrementing clock is generated. Do
not use this setting.
Clearing is disabled
Cleared by compare match A
Cleared by compare match B/input capture B
Cleared by input capture B
Rev. 4.00 Jan 26, 2006 page 851 of 938
8-bit timer channel 2
8-bit timer channel 3
0
CKS0
0
R/W
Description
REJ09B0276-0400