Renesas H8/3067 Series User Manual page 294

Section 8 I/O Ports
Table 8.1 Port Functions (1)
Port Description Pins
Port 1 • 8-bit I/O port
P1
7
• Can drive LEDs
A to A
7
Port 2 • 8-bit I/O port
P2
7
• Built-in input
A
15
pull-up
transistors
• Can drive LEDs
Port 3 • 8-bit I/O port
P3
7
D
15
Port 4 • 8-bit I/O port
P4
7
• Built-in input
D to D
7
pull-up
transistors
Port 5 • 4-bit I/O port
P5
3
• Built-in input
A
19
pull-up
transistors
• Can drive LEDs
Port 6 • 8-bit I/O port
P6
7
P6
6
P6
5
P6
4
P6
3
P6
2
P6
1
P6
0
Port 7 • 8-bit I/O port
P7
7
P7
6
P7
5
AN
5
Port 8 • 5-bit I/O port
P8
4
• P8
to P8 have
2 0
Schmitt inputs
P8
3
CS
1
P8
2
P8
1
P8
0
/RFSH
Rev. 4.00 Jan 26, 2006 page 270 of 938
REJ09B0276-0400
Expanded Modes
Mode 1 Mode 2
to P1 / Address output pins (A
0
0
to P2 / Address output pins (A
0
to A
8
to P3 / Data input/output (D
0 15
to D
8
to P4 / Data input/output (D
0 7
8-bit bus mode: generic input/output
0
16-bit bus mode: data input/output
to P5 / Address output (A to A
0 19
to A
16
/φ Clock output (φ) and generic input
Bus control signal output (LWR, HWR, RD, AS)
/LWR
/HWR
/RD
/AS
Bus control signal input/output (BACK, BREQ, WAIT) and
/BACK
/BREQ 3-bit generic input/output
/WAIT
/AN /DA Analog input (AN , AN
7 1 7
/AN /DA from D/A converter, and generic input
6 0
to P7 / Analog input (AN to AN
0 5
to AN
0
/CS DDR = 0: generic input
0
DDR = 1 (reset value): CS
IRQ input, CS
/IRQ / output, external trigger input (ADTRG) to A/D converter,
3 3 1
/ADTRG and generic input
DDR = 0 (after reset): generic input
DDR = 1: CS
output
1
IRQ and IRQ input, CS
/IRQ /CS
2 2 2 1
/IRQ /CS DDR = 0 (reset value): generic input
1 3
DDR = 1: CS and CS
2
IRQ input, RFSH output, and generic input/output
/IRQ
0 0
Mode 3 Mode 4 Mode 5
to A ) Address output (A
7 0
A ) and generic input
0
DDR = 0:
generic input
DDR = 1:
address output
to A ) Address output (A
15 8
A ) and generic input
8
DDR = 0:
generic input
DDR = 1:
address output
to D )
8
to D ) and 8-bit generic input/output
0
) Address output (A
16
A ) and 4-bit
16
generic input
DDR = 0: generic input
DDR = 1: address output
) to A/D converter, analog output (DA
6
) to A/D converter, and generic input
0
DDR = 0 (reset value):
output generic input
0
DDR = 1: CS
and CS
output, and generic input*
2 3
output
3
Single-Chip Modes
Mode 6
to Generic input/output
7
to Generic input/output
15
Generic input/output
Generic input/output
to Generic input/output
19
Generic input/output
, DA )
1 0
Generic input/output
output
0
IRQ
input, external trigger
3
input (ADTRG) to A/D
converter, and generic
input/output
IRQ and IRQ
2 1
generic input/output
IRQ
input and generic
0
input/output
Mode 7
input and