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1.2
Block Diagram
Figure 1.1 shows an internal block diagram.
MD
2
MD
1
MD
0
EXTAL
XTAL
STBY
RES
FWE*/RESO
NMI
φ/P6
7
LWR/P6
6
HWR/P6
5
RD/P6
4
AS/P6
3
BACK/P6
2
BREQ/P6
1
WAIT/P6
0
CS
/P8
0
4
ADTRG/CS
/IRQ
/P8
1
3
3
CS
/IRQ
/P8
2
2
2
CS
/IRQ
/P8
3
1
1
RFSH/IRQ
/P8
0
0
Note: * Functions as RESO in the mask ROM versions, and as FWE in the flash memory and
flash memory R versions.
H8/300H CPU
Interrupt controller
ROM
(mask ROM or
flash memory)
RAM
16-bit timer unit
8-bit timer unit
Programmable
timing pattern
controller (TPC)
Port B
Port A
Figure 1.1 Block Diagram
Port 3
Port 4
Address bus
Data bus (upper)
Data bus (lower)
DMA controller
(DMAC)
Watchdog timer
(WDT)
Serial communication
interface
×
(SCI)
3 channels
A/D converter
D/A converter
Port 7
Rev. 4.00 Jan 26, 2006 page 7 of 938
Section 1 Overview
P5 /A
3
19
P5 /A
2
18
P5 /A
1
17
P5 /A
0
16
P2 /A
7
15
P2 /A
6
14
P2 /A
5
13
P2 /A
4
12
P2 /A
3
11
P2 /A
2
10
P2 /A
1
9
P2 /A
0
8
P1 /A
7
7
P1 /A
6
6
P1 /A
5
5
P1 /A
4
4
P1 /A
3
3
P1 /A
2
2
P1 /A
1
1
P1 /A
0
0
P9 /SCK /IRQ
5
1
5
P9 /SCK /IRQ
4
0
4
P9 /RxD
3
1
P9 /RxD
2
0
P9 /TxD
1
1
P9 /TxD
0
0
REJ09B0276-0400
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