System Control Register (Syscr) - Renesas H8S/2319 series Hardware Manual

3.2.2

System Control Register (SYSCR)

Bit : 7
—
Initial value : 0
R/W : R/W
Bit 7—Reserved: Only 0 should be written to this bit.
Bit 6—Reserved: This bit is always read as 0, and cannot be modified.
Bits 5 and 4—Interrupt Control Mode 1 and 0 (INTM1, INTM0): These bits select the control
mode of the interrupt controller. For details of the interrupt control modes, see section 5.4.1,
Interrupt Control Modes and Interrupt Operation.
Bit 5 Bit 4
INTM1 INTM0
0 0
1
1 0
1
Bit 3—NMI Edge Select (NMIEG): Selects the valid edge of the NMI interrupt input.
Bit 3
NMIEG Description
0 An interrupt is requested at the falling edge of NMI input
1 An interrupt is requested at the rising edge of NMI input
Bit 2—LWR Output Disable (LWROD): Enables or disables LWR output.
Bit 2
LWROD Description
PF3 is designated as LWR output pin
0
PF3 is designated as I/O port, and does not function as LWR output pin
1
Bit 1—Reserved: Only 0 should be written to this bit.
Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is
initialized when the reset state is released. It is not initialized in software standby mode.
6 5
— INTM1
0 0
— R/W
Interrupt Control
Mode Description
0 Control of interrupts by I bit
— Setting prohibited
2 Control of interrupts by I2 to I0 bits and IPR
— Setting prohibited
4 3
INTM0 NMIEG LWROD
0 0
R/W R/W
Rev. 5.00, 12/03, page 73 of 1088
2 1
— RAME
0 0
R/W R/W R/W
(Initial value)
(Initial value)
(Initial value)
0
1