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Appendix B Internal I/O Registers
TISRB—Timer Interrupt Status Register B
Bit:
Initial value:
Read/Write:
Input capture/compare match interrupt enable B0
0
1
Input capture/compare match interrupt enable B1
0
IMIB1 interrupt requested by IMFB1 flag is disabled
1
IMIB1 interrupt requested by IMFB1 is enabled
Input capture/compare match interrupt enable B2
0
IMIB2 interrupt requested by IMFB2 flag is disabled
1
IMIB2 interrupt requested by IMFB2 is enabled
Note : * Only 0 can be written, to clear the flag.
Rev. 4.00 Jan 26, 2006 page 836 of 938
REJ09B0276-0400
7
6
IMIEB2
IMIEB1
1
0
R/W
R/W
Input capture/compare match flag B0
[Clearing condition]
0
Read IMFB0 when IMFB0=1, then write 0 in IMFB0.
[Setting conditions]
TCNT0=GRB0 when GRB0 functions as an output compare register.
1
TCNT0 value is transferred to GRB0 by an input capture signal when GRB0
functions as an input capture register.
Input capture/compare match flag B1
[Clearing condition]
0
Read IMFB1 when IMFB1=1, then write 0 in IMFB1.
[Setting conditions]
TCNT1=GRB1 when GRB1 functions as an output compare register.
1
TCNT1 value is transferred to GRB1 by an input capture signal when GRB1
functions as an input capture register.
Input capture/compare match flag B2
[Clearing condition]
0
Read IMFB2 when IMFB2=1, then write 0 in IMFB2.
[Setting conditions]
TCNT2=GRB2 when GRB2 functions as an output compare register.
1
TCNT2 value is transferred to GRB2 by an input capture signal when GRB2
functions as an input capture register.
IMIB0 interrupt requested by IMFB0 flag is disabled
IMIB0 interrupt requested by IMFB0 is enabled
H'FFF65
5
4
3
2
IMIEB0
IMFB2
IMFB1
0
0
1
0
R/W
R/(W)*
R/(W)*
(Initial value)
(Initial value)
16-bit timer (all channels)
1
0
IMFB0
0
0
R/(W)*
(Initial value)
(Initial value)
(Initial value)
(Initial value)
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