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Section 9 16-Bit Timer
Contention between TCNT Byte Write and Increment: If an increment pulse occurs in the T
or T
state of a TCNT byte write cycle, writing takes priority and TCNT is not incremented. The
3
TCNT byte that was not written retains its previous value. See figure 9.39, which shows an
increment pulse occurring in the T
φ
Address bus
Internal write signal
TCNT input clock
TCNTH
TCNTL
Figure 9.39 Contention between TCNT Byte Write and Increment
Rev. 4.00 Jan 26, 2006 page 386 of 938
REJ09B0276-0400
state of a byte write to TCNTH.
2
TCNTH byte write cycle
T
1
TCNTH address
N
TCNT write data
X
T
T
2
3
M
X + 1
X
2
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