Table of Contents
Advertisement
Figure 7.14 shows the timing when the DMAC is activated by low input at a DREQ pin. This
example shows a word-size transfer from a 16-bit two-state access area to another 16-bit two-state
access area. The DMAC continues the transfer while the DREQ pin is held low.
CPU cycle
T
T
1
2
φ
DREQ
Address
bus
RD
HWR
LWR
,
TEND
Figure 7.14 Bus Timing of DMA Transfer Requested by Low DREQ
DMAC cycle
T
T
T
T
T
3
d
1
2
1
Source
Destination
address
address
DMAC cycle
CPU cycle
(last transfer cycle)
T
T
T
T
T
2
1
2
d
1
Rev. 4.00 Jan 26, 2006 page 251 of 938
Section 7 DMA Controller
CPU cycle
T
T
T
T
2
1
2
1
Source
Destination
address
address
DREQ
DREQ
DREQ Input
REJ09B0276-0400
T
2
Advertisement
Table of Contents
