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Section 9 16-Bit Timer
Table 9.7 (b) 16-bit timer Operating Modes (Channel 1)
Operating Mode
Synchronous preset
PWM mode
Output compare A
Output compare B
Input capture A
Input capture B
Counter By compare
clearing match/input
capture A
By compare
match/input
capture B
Syn-
chronous
clear
Setting available (valid). Setting does not affect this mode.
Legend:
Notes:
The input capture function cannot be used in PWM mode. If compare match A and compare match B
*
occur simultaneously, the compare match signal is inhibited.
Rev. 4.00 Jan 26, 2006 page 394 of 938
REJ09B0276-0400
TSNC
TMDR
Synchro-
nization
MDF
FDIR PWM
SYNC1 = 1
SYNC1 = 1
Register Settings
TIOR1
IOA
IOB
PWM1 = 1
PWM1 = 0
IOA2 = 0
Other bits
unrestricted
IOB2 = 0
Other bits
unrestricted
PWM1 = 0
IOA2 = 1
Other bits
unrestricted
PWM1 = 0
IOB2 = 1
Other bits
unrestricted
TCR1
Clear
Clock
Select
Select
*
CCLR1 = 0
CCLR0 = 1
CCLR1 = 1
CCLR0 = 0
CCLR1 = 1
CCLR0 = 1
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