Renesas H8/3067 Series User Manual page 301

In modes 1 to 4, P2DDR bits are always read as 1, and cannot be modified.
In modes 5 to 7, P2DDR is a write-only register. Its value cannot be read. All bits return 1 when
read.
P2DDR is initialized to H'FF in modes 1 to 4, and to H'00 in modes 5 to 7, by a reset and in
hardware standby mode. In software standby mode it retains its previous setting. Therefore, if a
transition is made to software standby mode while port 2 is functioning as an input/output port and
a P2DDR bit is set to 1, the corresponding pin maintains its output state.
Port 2 Data Register (P2DR): P2DR is an 8-bit readable/writable register that stores output data
for Port 2. When port 2 functions as an output port, the value of this register is output. When a bit
in P2DDR is set to 1, if port 2 is read the value of the corresponding P2DR bit is returned. When a
bit in P2DDR is cleared to 0, if port 2 is read the corresponding pin logic level is read.
Bit 7
P2
Initial value 0
Read/Write R/W
P2DR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting.
Port 2 Input Pull-Up MOS Control Register (P2PCR): P2PCR is an 8-bit readable/writable
register that controls the MOS input pull-up transistors in port 2.
Bit 7
P2 PCR
7
Initial value 0
Read/Write R/W
In modes 5 to 7, when a P2DDR bit is cleared to 0 (selecting generic input), if the corresponding
bit in P2PCR is set to 1, the input pull-up transistor is turned on.
6 5
P2 P2
7 6 5
0 0
R/W R/W
Port 2 data 7 to 0
These bits store data for port 2 pins
6 5
P2 PCR P2 PCR
6 5
0 0
R/W R/W
Port 2 input pull-up MOS control 7 to 0
These bits control input pull-up
transistors built into port 2
4 3
P2 P2
4 3
0 0
R/W R/W
4 3
P2 PCR P2 PCR P2 PCR
4 3
0 0
R/W R/W
Rev. 4.00 Jan 26, 2006 page 277 of 938
Section 8 I/O Ports
2 1
P2 P2 P2
2 1
0 0
R/W R/W R/W
2 1
P2 PCR P2 PCR
2 1 0
0 0
R/W R/W R/W
REJ09B0276-0400
0
0
0
0
0