Renesas H8/3067 Series User Manual page 444

Renesas 16-bit single-chip microcomputer
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Section 10 8-Bit Timers
16-Bit Count Mode
• Channels 0 and 1:
When bits CKS2 to CKS0 are set to B'100 in TCR0, the timer functions as a single 16-bit timer
with channel 0 occupying the upper 8 bits and channel 1 occupying the lower 8 bits.
 Setting when Compare Match Occurs
• The CMF flag is set to 1 in TCR0 when a 16-bit compare match occurs.
• The CMF flag is set to 1 in TCR1 when a lower 8-bit compare match occurs.
• TMO
pin output control by bits OIS3, OIS2, OS1, and OS0 in TCSR0 is in accordance
0
with the 16-bit compare match conditions.
• TMIO
pin output control by bits OIS3, OIS2, OS1, and OS0 in TCSR1 is in
1
accordance with the lower 8-bit compare match conditions.
 Setting when Input Capture Occurs
• The CMFB flag is set to 1 in TCR0 and TCR1 when the ICE bit is 1 in TCSR1 and
input capture occurs.
• TMIO
pin input capture input signal edge detection is selected by bits OIS3 and OIS2
1
in TCSR0.
 Counter Clear Specification
• If counter clear on compare match or input capture has been selected by the CCLR1 and
CCLR0 bits in TCR0, the 16-bit counter (both TCNT0 and TCNT1) is cleared.
• The settings of the CCLR1 and CCLR0 bits in TCR1 are ignored. The lower 8 bits
cannot be cleared independently.
 OVF Flag Operation
• The OVF flag is set to 1 in TCSR0 when the 16-bit counter (TCNT0 and TCNT1)
overflows (from H'FFFF to H'0000).
• The OVF flag is set to 1 in TCSR1 when the 8-bit counter (TCNT1) overflows (from
H'FF to H'00).
• Channels 2 and 3:
When bits CKS2 to CKS0 are set to B'100 in TCR2, the timer functions as a single 16-bit timer
with channel 2 occupying the upper 8 bits and channel 3 occupying the lower 8 bits.
 Setting when Compare Match Occurs
• The CMF flag is set to 1 in TCR2 when a 16-bit compare match occurs.
• The CMF flag is set to 1 in TCR3 when a lower 8-bit compare match occurs.
• TMO
pin output control by bits OIS3, OIS2, OS1, and OS0 in TCSR2 is in accordance
2
with the 16-bit compare match conditions.
• TMIO
pin output control by bits OIS3, OIS2, OS1, and OS0 in TCSR3 is in
3
accordance with the lower 8-bit compare match conditions.
Rev. 4.00 Jan 26, 2006 page 420 of 938
REJ09B0276-0400

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H8/3067H8/3066H8/3065H8/3067rf

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