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Appendix B Internal I/O Registers
ADCSR—A/D Control/Status Register
7
Bit
ADF
ADIE
Initial value
0
Read/Write
R/(W)*
R/W
A/D interrupt enable
0
1
A/D end flag
[Clearing condition]
0
Read ADF when ADF = 1, then write 0 in ADF
The DMAC is activated by an ADI interrupt
1
[Setting conditions]
Single mode: A/D conversion ends
Scan mode: A/D conversion ends in all selected channels
Note: * Only 0 can be written, to clear the flag.
Rev. 4.00 Jan 26, 2006 page 878 of 938
REJ09B0276-0400
6
5
4
ADST
SCAN
CKS
0
0
0
R/W
R/W
R/W
Clock select
Conversion time =
0
134 states (maximum)
Conversion time =
1
70 states (maximum)
Scan mode
0
Single mode
1
Scan mode
A/D start
0
A/D conversion is stopped
Single mode: A/D conversion starts; ADST is automatically cleared to 0 when conversion ends
1
Scan mode: A/D conversion starts and continues, cycling among the selected channels ADST
is cleared to 0 by software, by a reset, or by a transition to standby mode
A/D end interrupt request is disabled
A/D end interrupt request is enabled
3
2
1
CH2
CH1
CH0
0
0
0
R/W
R/W
R/W
Channel select 2 to 0
Group Selection
CH2
0
1
H'FFFE8
A/D
0
0
Description
Channel Selection
CH1 CH0
Single Mode
Scan Mode
0
AN
AN
0
0
1
AN
AN
1
0
AN
AN
2
1
1
AN
AN
3
0
AN
AN
4
0
1
AN
AN
5
0
AN
AN
6
1
1
AN
AN
7
0
AN
0,
1
to AN
0
2
to AN
0
3
4
AN
4,
5
to AN
4
6
to AN
4
7
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