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Section 6 Bus Controller
φ
Address bus
CS
(RAS)
n
PB
(UCAS)
4
PB
(LCAS)
5
RD(WE)
RFSH
RFSH): A refresh signal (RFSH) that transmits a refresh cycle off-chip can be
RFSH
RFSH
Refresh Signal (RFSH
output by setting the RFSHE bit to 1 in DRCRA. RFSH output timing is shown in figures 6.28,
6.29, and 6.30.
6.5.12
Examples of Use
Examples of DRAM connection and program setup procedures are shown below. When the
DRAM interface is used, check the DRAM device characteristics and choose the most appropriate
method of use for that device.
Connection Examples
• Figure 6.31 shows typical interconnections when using two 2-CAS type 16-Mbit DRAMs
using a × 16-bit organization, and the corresponding address map. The DRAMs used in this
example are of the 10-bit row address × 10-bit column address type. Up to four DRAMs can be
connected by designating areas 2 to 5 as DRAM space.
Rev. 4.00 Jan 26, 2006 page 184 of 938
REJ09B0276-0400
Software standby
mode
High-impedance
Figure 6.30 Self-Refresh Timing (CSEL = 0)
Oscillation stabilization
time
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