T
1
φ
t
AD
A
to A
23
3
CSn
A
to A
2
0
t
ASD
AS
t
AS1
t
ASD
RD
t
AS1
D
to D
15
0
Note:
Specification from the earliest negation timing of A
*
Figure 21.14 Burst ROM Access Timing: Two-State Access
T
T
2
3
t
t
ACC4
SD
t
ACC4
t
t
ACC2
RDS
Section 21 Electrical Characteristics
T
1
t
AD
t
t
ASD
AH
t
AS1
t
ACC1
to A
, CSn, and RD.
23
0
Rev. 4.00 Jan 26, 2006 page 743 of 938
T
2
t
t
SD
AH
t
RSD
t
*
RDH
t
RDS
REJ09B0276-0400