Page 1 Details should always be checked by referring to the relevant text. H8/38024, H8/38024S, H8/38024R, H8/38124 Group Hardware Manual Renesas 8-Bit Single-Chip Microcomputer H8 Family/H8/300L Super Low Power Series H8/38024 Group H8/38024 H8/38024R Group H8/38024R H8/38023 H8/38124 Group...
Page 2 (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp.
Page 3 General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed.
Page 4 Configuration of This Manual This manual comprises the following items: 1. General Precautions on Handling of Product 2. Configuration of This Manual 3. Preface 4. Contents 5. Overview 6. Description of Functional Modules • CPU and System-Control Modules • On-Chip Peripheral Modules The configuration of the functional description of each module differs according to the module.
Page 5 Below is a table listing the product specifications for each group. Notes: 1. F-ZTAT is a trademark of Renesas Technology Corp. 2. ZTAT is a trademark of Renesas Technology Corp. Rev. 7.00 Mar 10, 2005 page v of xlii...
Page 6 Specifications H8/38024R H8/38024S H8/38024 Group H8/38124 Group Group Group Item ZTAT Mask Flash Flash Mask Flash Mask Memory 32 Kbytes 8 Kbytes 32 Kbytes 32 Kbytes 8 Kbytes to 16 Kbytes/ 8 Kbytes 32 Kbytes 32 Kbytes 32 Kbytes 32 Kbytes 1 Kbyte 512 bytes 1 Kbyte...
Page 7 Explanatory Note: Bit sequence: upper bit at left, and lower bit at right List of Related Documents: The latest documents are available on our Web site. Please make sure that you have the latest version. (http://www.renesas.com/) • User manual for H8/38024 Group, H8/38024S Group, H8/38024R Group, and H8/38124 Group Name of Document Document No.
Page 8 • Application note Name of Document Document No. H8/300 Series, H8/300L Series software ADE-502-052 Notes: The following limitations apply to H8/38024, H8/38024R, and H8/38124 programming and debugging when the on-chip emulator is used. 1. Pin 95 is not available because it is used exclusively by the on-chip emulator. 2.
Page 9 Main Revisions in This Edition Item Page Revision (See Manual for Details) Product name amended H8/38024F-ZTAT → H8/38024R Group Product name added HD64F38122 Preface Table amended Specifications H8/38124 Group Item Flash Mask Memory 16 Kbytes/ 8 Kbytes 32 Kbytes 32 Kbytes 1 Kbyte 512 bytes 1 Kbyte...
Page 10 Item Page Revision (See Manual for Details) 1.1 Overview 3, 6 Table amended Table 1.1 Features Item Specification Clock pulse Two on-chip clock pulse generators generators • System clock pulse generator: 1.0 to 16 MHz: H8/38024 Group 1.0 to 10 MHz: HD64F38024, HD64F38024R, and H8/38024S Group 2.0 to 20 MHz: H8/38124 Group •...
Page 11 Item Page Revision (See Manual for Details) 1.3.1 Pin Title amended Arrangement Figure 1.4 Pin Arrangement (TLP- 85V, H8/38024R Group, H8/38024S Group) 1.3.2 Pin Functions 20, 24 Table amended and note 5 added Table 1.5 Pin Pin No. FP-80A Functions No.
Page 12 Item Page Revision (See Manual for Details) 3.3.2 Interrupt Table amended Control Registers Setting conditions: Interrupt Request When the timer C counter value overflows or underflows Register 2 (IRR2) Bit 1 Table and notes amended 4.2 System Clock Generator Connecting a Ceramic C 1 , C 2 Ceramic Oscillator...
Page 13 Item Page Revision (See Manual for Details) 5.1 Overview Notes amended Figure 5.1 Mode Notes: 1. A transition between different modes cannot be Transition Diagram made to occur simply because an interrupt request is generated. Make sure that interrupts are enabled. 5.1.1 System Control Note amended Registers...
Page 14 Item Page Revision (See Manual for Details) 6.5.1 Features Description and note amended The features of the 32-Kbyte or 16-Kbyte flash memory built into the flash memory versions are summarized below. • Programming/erase methods — The flash memory is programmed 128 bytes at a time. Erase is performed in single-block units.
Page 15 Item Page Revision (See Manual for Details) 6.5.3 Block Figure title amended Configuration Figure 6.8(1) Block Configuration of 32-kbyte Flash Memory Figure 6.8(2) Block Newly added Configuration of 16-kbyte Flash Memory 6.6.3 Erase Block Table amended Register (EBR) Bit Name Block (Size) Address Table 6.6 Division of...
Page 16 Item Page Revision (See Manual for Details) 6.8.1 Program/ Description amended Program-Verify 4. Consecutively transfer 128 bytes of data in byte units from the reprogramming data area or additional-programming data area to the flash memory. The program address and 128-byte data are latched in the flash memory.
Page 17 Item Page Revision (See Manual for Details) 7.1 Overview Note deleted 8.2.2 Register Note amended Configuration and Note: * Pin 1 and the associated function are not Description implemented on the H8/38124 Group. The register is both Port Data Register 1 readable and writeable.
Page 18 Item Page Revision (See Manual for Details) 9.7.5 Application Description amended Notes 2. Use a clock with a frequency of up to 16 MHz for input to the AEVH and AEVL pins, and ensure that the high and low widths of the clock are at least half the OSC clock cycle duration.
Page 19 Item Page Revision (See Manual for Details) 10.2.8 Bit Rate Table amended Register (BRR) Setting Maximum Bit Rate φ φ φ φ (MHz) Table 10.5 Maximum OSC (MHz) (bit/s) 0.0384 * Bit Rate for Each 0.0192 31250 Frequency 2.4576 1.2288 38400 (Asynchronous Mode) 62500...
Page 20 Item Page Revision (See Manual for Details) 10.3.3 Operation in Figure amended Synchronous Mode Serial • Receiving clock Serial Figure 10.14 Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 data Example of Operation when Receiving in 1 frame 1 frame Synchronous Mode...
Page 21 Item Page Revision (See Manual for Details) 16.1 H8/38024 Title amended Group ZTAT Version and Mask ROM Version Absolute Maximum Ratings 16.2 H8/38024 Title amended Group ZTAT Version and Mask ROM Version Electrical Characteristics Title amended 16.3 H8/38024 Group F-ZTAT Version and H8/38024R Group F-ZTAT Version...
Page 22 Item Page Revision (See Manual for Details) 16.8.1 Power Supply Figure amended Voltage and Operating Ranges 20.0 Power Supply Voltage and Oscillation Frequency Range (System Clock Oscillator Selected) • Active (high-speed) mode • Sleep (high-speed) mode Power Supply Voltage Figure amended and Operating Frequency Range 10.0...
Page 23 Item Page Revision (See Manual for Details) 16.8.1 Power Supply Figure amended Voltage and Operating Ranges 10.0 Analog Power Supply Voltage and A/D Converter Operating Range (System Clock Oscillator Selected) • Active (high-speed) mode • Sleep (high-speed) mode 16.8.2 DC 512, 513 Table amended Characteristics...
Page 24 Item Page Revision (See Manual for Details) 16.8.2 DC Values Characteristics Item Symbol Applicable Pins Unit Test Condition Notes Active — — Active (medium- OPE2 Table 16.21 DC mode speed) mode Approx. current = 2.7 V, max. value Characteristics = 1.1 × consump- = 2 MHz, φ...
Page 25 Item Page Revision (See Manual for Details) 16.8.2 DC 515, 516 Values Characteristics Item Symbol Applicable Pins Unit Test Condition Notes Sleep — — = 2.7 V, SLEEP Table 16.21 DC mode = 2 MHz Approx. current max. value Characteristics = 1.1 ×...
Page 26 When designing systems, make sure to give due consideration to the SPEC range. Please contact a Renesas sales or support representative for actual performance data on the product. Rev. 7.00 Mar 10, 2005 page xxvi of xlii...
Page 27 Item Page Revision (See Manual for Details) 16.8.3 AC Table amended Characteristics Values Table 16.23 Serial Item Symbol Interface (SCI3) Timing Input clock Asynchronous scyc cycle Clocked synchronous Input clock pulse width SCKW Transmit data delay time — (clocked synchronous) Receive data setup time 150.0 (clocked synchronous)
Page 28 Item Page Revision (See Manual for Details) B.2 Functions Clock Select and notes amended AMR—A/D Mode Clock Select Register Bit 7 Conversion Time φ = 10 MHz * φ = 1 MHz φ = 5 MHz Conversion Period 62 µs 12.4 µs 6.2 µs 62/φ...
Page 29 Item Page Revision (See Manual for Details) Appendix E List of Table amended Product Codes Package Product Type Product Code Mark Code (Package Code) Table E.1 H8/38024 H8/38124 H8/38124 Mask ROM Regular HD64338124H 38124(***)H 80-pin QFP (FP-80A) Group versions specifications Group Product Code HD64338124W 38124(***)W...
Page 30 Rev. 7.00 Mar 10, 2005 page xxx of xlii...
Page 31: Table Of Contents
Contents Section 1 Overview ......................Overview........................... Internal Block Diagram..................... Pin Arrangement and Functions..................1.3.1 Pin Arrangement....................1.3.2 Pin Functions ....................... 19 Section 2 CPU ........................25 Overview........................... 25 2.1.1 Features........................ 25 2.1.2 Address Space...................... 26 2.1.3 Register Configuration..................26 Register Descriptions......................27 2.2.1 General Registers....................
Page 32 2.7.2 Program Execution State ..................59 2.7.3 Program Halt State....................59 2.7.4 Exception-Handling State ..................59 Memory Map ........................60 2.8.1 Memory Map ....................... 60 Application Notes ......................66 2.9.1 Notes on Data Access ..................66 2.9.2 Notes on Bit Manipulation................... 68 2.9.3 Notes on Use of the EEPMOV Instruction ............
Page 33 4.5.3 Note on Use of HD64F38024 ................118 Notes on H8/38124 Group....................118 Section 5 Power-Down Modes ..................119 Overview........................... 119 5.1.1 System Control Registers ..................122 Sleep Mode ........................126 5.2.1 Transition to Sleep Mode..................126 5.2.2 Clearing Sleep Mode ................... 127 5.2.3 Clock Frequency in Sleep (Medium-Speed) Mode..........
Page 34 Section 6 ROM ........................143 Overview........................... 143 6.1.1 Block Diagram..................... 143 H8/38024 PROM Mode....................144 6.2.1 Setting to PROM Mode ..................144 6.2.2 Socket Adapter Pin Arrangement and Memory Map........... 144 H8/38024 Programming....................147 6.3.1 Writing and Verifying..................147 6.3.2 Programming Precautions..................
Page 35 6.10.7 Status Polling ....................... 187 6.10.8 Programmer Mode Transition Time ..............188 6.10.9 Notes on Memory Programming ................. 188 6.11 Power-Down States for Flash Memory................189 Section 7 RAM ........................191 Overview........................... 191 7.1.1 Block Diagram..................... 191 Section 8 I/O Ports ......................
Page 36 Port 7..........................222 8.7.1 Overview......................222 8.7.2 Register Configuration and Description .............. 222 8.7.3 Pin Functions ....................... 224 8.7.4 Pin States ......................224 Port 8..........................225 8.8.1 Overview......................225 8.8.2 Register Configuration and Description .............. 225 8.8.3 Pin Functions ....................... 227 8.8.4 Pin States ......................
Page 37 9.3.1 Overview......................253 9.3.2 Register Descriptions................... 255 9.3.3 Timer Operation ....................258 9.3.4 Timer C Operation States ..................260 Timer F ..........................261 9.4.1 Overview......................261 9.4.2 Register Descriptions................... 264 9.4.3 CPU Interface ...................... 271 9.4.4 Operation ......................274 9.4.5 Application Notes ....................
Page 38 10.2.5 Serial Mode Register (SMR) ................337 10.2.6 Serial Control Register 3 (SCR3) ................ 340 10.2.7 Serial Status Register (SSR) ................344 10.2.8 Bit Rate Register (BRR) ..................348 10.2.9 Clock stop register 1 (CKSTPR1) ............... 354 10.2.10 Serial Port Control Register (SPCR)..............354 10.3 Operation ..........................
Page 39 12.3.1 A/D Conversion Operation .................. 406 12.3.2 Start of A/D Conversion by External Trigger Input ..........406 12.3.3 A/D Converter Operation Modes................. 407 12.4 Interrupts........................... 407 12.5 Typical Use........................407 12.6 A/D Conversion Accuracy Definitions ................411 12.7 Application Notes ......................413 12.7.1 Permissible Signal Source Impedance ..............
Page 40 14.3 Operation .......................... 443 14.3.1 Power-On Reset Circuit..................443 14.3.2 Low-Voltage Detection Circuit ................444 Section 15 Power Supply Circuit (H8/38124 Group Only) ........451 15.1 When Using Internal Power Supply Step-Down Circuit ..........451 15.2 When Not Using Internal Power Supply Step-Down Circuit..........452 Section 16 Electrical Characteristics ................
Page 41 16.8.4 A/D Converter Characteristics................521 16.8.5 LCD Characteristics..................... 522 16.8.6 Flash Memory Characteristics ................523 16.8.7 Power Supply Voltage Detection Circuit Characteristics ........525 16.8.8 Power-On Reset Circuit Characteristics .............. 528 16.8.9 Watchdog Timer Characteristics ................. 529 16.9 Operation Timing......................529 16.10 Output Load Circuit ......................
Page 42 Appendix H Form of Bonding Pads ................649 Appendix I Specifications of Chip Tray ..............650 Rev. 7.00 Mar 10, 2005 page xlii of xlii...
Page 43: Section 1 Overview
Table 1.1 summarizes the features of the H8/38024 Group, H8/38024S Group, and H8/38124 Group. Notes: 1. ZTAT (Zero Turn Around Time) is a trademark of Renesas Technology Corp. 2. F-ZTAT is a trademark of Renesas Technology Corp. Rev. 7.00 Mar 10, 2005 page 1 of 652...
Page 44 Section 1 Overview Table 1.1 Features Item Specification High-speed H8/300L CPU • General-register architecture General registers: Sixteen 8-bit registers (can be used as eight 16-bit registers) • Operating speed  Max. operating speed: 8 MHz (5 MHz for HD64F38024 and H8/38024S Group) ...
Page 45 Section 1 Overview Item Specification Clock pulse Two on-chip clock pulse generators generators • System clock pulse generator: 1.0 to 16 MHz: H8/38024 Group 1.0 to 10 MHz: HD64F38024, HD64F38024R, and H8/38024S Group 2.0 to 20 MHz: H8/38124 Group • Subclock pulse generator: 32.768 kHz, 38.4 kHz* (* does not apply to H8/38124 Group) H8/38124 Group equipped with on-chip oscillator...
Page 46 Section 1 Overview Item Specification Timers Six on-chip timers • Timer A: 8-bit timer Count-up timer with selection of eight internal clock signals divided from the system clock (φ) * and four clock signals divided from the watch clock (φ •...
Page 47 Section 1 Overview Item Specification • Serial SCI3: 8-bit synchronous/asynchronous serial interface communication Incorporates multiprocessor communication function interface 10-bit PWM Pulse-division PWM output for reduced ripple • Can be used as a 10-bit D/A converter by connecting to an external low- pass filter.
Page 48 Section 1 Overview Item Specification Product lineup Product Code ROM/RAM Size Mask ROM Version ZTAT Version F-ZTAT Version Package (Byte) HD64338024 HD64738024 HD64F38024R FP-80A 32K/1K FP-80B HD64F38024 TFP-80C TLP-85V (HD64F38024R only) Die (mask ROM/F-ZTAT version only) HD64338023 — — FP-80A 24K/1K FP-80B TFP-80C...
Page 49: Internal Block Diagram
Section 1 Overview Internal Block Diagram Figure 1.1(1) shows a block diagram of the H8/38024 Group and H8/38024S Group. Figure 1.1(2) shows a block diagram of the H8/38124 Group. = AV Sub clock H8/300L TEST IRQAEC Asynchronous System clock /COM counter /COM (16 bits)
Page 50 Section 1 Overview = AV Sub clock H8/300L TEST IRQAEC /COM Asynchronous System clock /COM counter (16 bits) /COM /COM /TMIG /IRQ /ADTRG (8 Kbytes to 32 Kbytes) 10-bit PWM1 Power-on reset and /IRQ /TMIF low-voltage detect circuits /PWM /PWM /TMOFL /TMOFH /SEG...
Page 51: Pin Arrangement And Functions
Section 1 Overview Pin Arrangement and Functions 1.3.1 Pin Arrangement The H8/38024 Group, H8/38024R Group, H8/38024S Group, and H8/38124 Group pin arrangements are shown in figures 1.2, 1.3, and 1.4. The bonding pad location diagram of the HCD64338024, HCD64338023, HCD64338022, HCD64338021, and HCD64338020 is shown in figure 1.5.
Page 52 Section 1 Overview /SEG /SEG /TMOFL /TMOFH /SEG /SEG /SEG /SEG /SEG /AEVH /AEVL /SEG /SCK /SEG /RXD FP-80A,TFP-80C /SEG /SEG /TXD (Top view) /IRQ /SEG /extD /SEG /extU /SEG /SEG /SEG /IRQ /TMIC /SEG /SEG /SEG /SEG Note: If the on-chip emulator is used, pins 95, 33, 34, and 35 are reserved for the emulator and not available to the user. Figure 1.2(2) Pin Arrangement (FP-80A, TFP-80C: Top View, H8/38124 Group) Rev.
Page 53 Section 1 Overview /SEG /TMOFH /SEG /SEG /SEG /SEG /AEVH /SEG /AEVL /SEG /SCK FP-80B /SEG /RXD (Top view) /SEG /TXD /SEG /IRQ /SEG /SEG /SEG /SEG /IRQ /TMIC /SEG /SEG Note: If the on-chip emulator is used, pins 95, 33, 34, and 35 are reserved for the emulator and not available to the user. Figure 1.3 Pin Arrangement (FP-80B: Top View, H8/38024 Group, H8/38024R Group) Rev.
Page 54 Section 1 Overview TLP-85V (Top view) Note: Pins are shown in transparent view. Figure 1.4 Pin Arrangement (TLP-85V, H8/38024R Group, H8/38024S Group) Rev. 7.00 Mar 10, 2005 page 12 of 652 REJ09B0042-0700...
Page 55 Section 1 Overview Type code (0, 0) Chip size: 3.99 mm × 3.99 mm Voltage level on the back of the chip: GND Figure 1.5 Bonding Pad Location Diagram of HCD64338024, HCD64338023, HCD64338022, HCD64338021, and HCD64338020 (Top View) Rev. 7.00 Mar 10, 2005 page 13 of 652 REJ09B0042-0700...
Page 56 Section 1 Overview Table 1.2 Bonding Pad Coordinates of HCD64338024, HCD64338023, HCD64338022, HCD64338021, and HCD64338020 Coordinates Coordinates X (µ µ µ µ m) Y (µ µ µ µ m) X (µ µ µ µ m) Y (µ µ µ µ m) Pad No.
Page 57 Section 1 Overview (0, 0) Type code 34 36 38 35 37 Chip size: 3.84 mm × 4.24 mm Voltage level on the back of the chip: GND : NC pad Figure 1.6 Bonding Pad Location Diagram of HCD64F38024, HCD64F38024R (Top View) Rev.
Page 58 Section 1 Overview Table 1.3 Bonding Pad Coordinates of HCD64F38024, HCD64F38024R Coordinates Coordinates X (µ µ µ µ m) Y (µ µ µ µ m) X (µ µ µ µ m) Y (µ µ µ µ m) Pad No. Pad Name Pad No.
Page 59 Section 1 Overview (0.0) Chip size: 2.91 mm × 2.91 mm Voltage level on the back of the chip: GND Figure 1.7 Bonding Pad Location Diagram of HCD64338024S, HCD64338023S, HCD64338022S, HCD64338021S, and HCD64338020S (Top View) Rev. 7.00 Mar 10, 2005 page 17 of 652 REJ09B0042-0700...
Page 60 Section 1 Overview Table 1.4 Bonding Pad Coordinates of HCD64338024S, HCD64338023S, HCD64338022S, HCD64338021S, and HCD64338020S Coordinates Coordinates X (µ µ µ µ m) Y (µ µ µ µ m) X (µ µ µ µ m) Y (µ µ µ µ m) Pad No.
Page 61: Pin Functions
Section 1 Overview 1.3.2 Pin Functions Table 1.5 outlines the pin functions of the H8/38024 Group. Table 1.5 Pin Functions Pin No. FP-80A No. * No. * No. * Type Symbol TFP-80C FP-80B TLP-85V Name and Functions Power Input Power supply: All V source pins should be connected pins...
Page 62 Section 1 Overview Pin No. FP-80A No. * No. * No. * Type Symbol TFP-80C FP-80B TLP-85V Name and Functions Input Clock These pins connect to a pins crystal or ceramic Output oscillator, or can be used to input an external clock. See section 4, Clock Pulse Generators, for a typical connection...
Page 63 Section 1 Overview Pin No. FP-80A No. * No. * No. * Type Symbol TFP-80C FP-80B TLP-85V Name and Functions 20 to 13 22 to 15 H1, J1, Input Interrupt 21 to 22 to 20 to Wakeup interrupt W K P pins H3, G1, request 7 to 0: These are...
Page 64 Section 1 Overview Pin No. FP-80A No. * No. * No. * Type Symbol TFP-80C FP-80B TLP-85V Name and Functions Output 10-bit PWM output: 10-bit PWM1 PWM pin PWM2 These are output pins for waveforms generated by the channel 1 and 2 10-bit PWMs.
Page 65 Section 1 Overview Pin No. FP-80A No. * No. * No. * Type Symbol TFP-80C FP-80B TLP-85V Name and Functions I/O ports 36 to 29 38 to 41 J8, J7 37 to 38 to 36 to Port 7: This is an 8-bit I/O K6, H7 port.
Page 66 Section 1 Overview Pin No. FP-80A No. * No. * No. * Type Symbol TFP-80C FP-80B TLP-85V Name and Functions Input A/D converter trigger A D T R G converter input: This is the external trigger input pin to the A/D converter.
Page 67: Section 2 Cpu
Section 2 CPU Section 2 CPU Overview The H8/300L CPU has sixteen 8-bit general registers, which can also be paired as eight 16-bit registers. Its concise instruction set is designed for high-speed operation. 2.1.1 Features Features of the H8/300L CPU are listed below. •...
Page 68: Address Space
Section 2 CPU 2.1.2 Address Space The H8/300L CPU supports an address space of up to 64 Kbytes for storing program code and data. See section 2.8, Memory Map, for details of the memory map. 2.1.3 Register Configuration Figure 2.1 shows the register structure of the H8/300L CPU. There are two groups of registers: the general registers and control registers.
Page 69: Register Descriptions
Section 2 CPU Register Descriptions 2.2.1 General Registers All the general registers can be used as both data registers and address registers. When used as data registers, they can be accessed as 16-bit registers (R0 to R7), or the high bytes (R0H to R7H) and low bytes (R0L to R7L) can be accessed separately as 8-bit registers.
Page 70 Section 2 CPU Condition Code Register (CCR) This 8-bit register contains internal status information, including the interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. These bits can be read and written by software (using the LDC, STC, ANDC, ORC, and XORC instructions). The N, Z, V, and C flags are used as branching conditions for conditional branching (Bcc) instructions.
Page 71: Initial Register Values
Section 2 CPU Refer to the H8/300L Series Programming Manual for the action of each instruction on the flag bits. 2.2.3 Initial Register Values When the CPU is reset, the program counter (PC) is initialized to the value stored at address H'0000 in the vector table, and the I bit in the CCR is set to 1.
Page 72: Data Formats In General Registers
Section 2 CPU 2.3.1 Data Formats in General Registers Data of all the sizes above can be stored in general registers as shown in figure 2.3. Data Type Register No. Data Format 1-bit data Don't care 1-bit data Don't care Byte data Don't care Byte data...
Page 73: Memory Data Formats
Section 2 CPU 2.3.2 Memory Data Formats Figure 2.4 indicates the data formats in memory. The H8/300L CPU can access word data stored in memory (MOV.W instruction), but the word data must always begin at an even address. If word data starting at an odd address is accessed, the least significant bit of the address is regarded as 0, and the word data starting at the preceding address is accessed.
Page 74: Addressing Modes
Section 2 CPU Addressing Modes 2.4.1 Addressing Modes The H8/300L CPU supports the eight addressing modes listed in table 2.1. Each instruction uses a subset of these addressing modes. Table 2.1 Addressing Modes Address Modes Symbol Register direct Register indirect Register indirect with displacement @(d:16, Rn) Register indirect with post-increment...
Page 75 Section 2 CPU Register Indirect with Post-Increment or Pre-Decrement—@Rn+ or @–Rn: • Register indirect with post-increment—@Rn+ The @Rn+ mode is used with MOV instructions that load registers from memory. The register field of the instruction specifies a 16-bit general register containing the address of the operand.
Page 76: Effective Address Calculation
Section 2 CPU The upper 8 bits of the absolute address are assumed to be 0 (H'00), so the address range is from H'0000 to H'00FF (0 to 255). Note that with the H8/300L Series, the lower end of the address area is also used as a vector area.
Page 77 Section 2 CPU Table 2.2 Effective Address Calculation Rev. 7.00 Mar 10, 2005 page 35 of 652 REJ09B0042-0700...
Page 78 Section 2 CPU Rev. 7.00 Mar 10, 2005 page 36 of 652 REJ09B0042-0700...
Page 79 Section 2 CPU Rev. 7.00 Mar 10, 2005 page 37 of 652 REJ09B0042-0700...
Page 80: Instruction Set
Section 2 CPU Instruction Set The H8/300L Series can use a total of 55 instructions, which are grouped by function in table 2.3. Table 2.3 Instruction Set Function Instructions Number MOV, PUSH * , POP * Data transfer Arithmetic operations ADD, SUB, ADDX, SUBX, INC, DEC, ADDS, SUBS, DAA, DAS, MULXU, DIVXU, CMP, NEG Logic operations...
Page 81 Section 2 CPU Notation General register (destination) General register (source) General register (EAd), <EAd> Destination operand (EAs), <EAs> Source operand Condition code register N (negative) flag of CCR Z (zero) flag of CCR V (overflow) flag of CCR C (carry) flag of CCR Program counter Stack pointer #IMM...
Page 82: Data Transfer Instructions
Section 2 CPU 2.5.1 Data Transfer Instructions Table 2.4 describes the data transfer instructions. Figure 2.5 shows their object code formats. Table 2.4 Data Transfer Instructions Size * Instruction Function (EAs) → Rd, Rs → (EAd) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register.
Page 83 Section 2 CPU Rm→Rn @Rm←→Rn @(d:16, Rm)←→Rn disp @Rm+→Rn, or Rn →@−Rm @aa:8←→Rn @aa:16←→Rn #xx:8→Rn #xx:16→Rn PUSH, POP → @SP+ Rn, or → @−SP [Legend] Operation field rm, rn: Register field disp: Displacement abs: Absolute address IMM: Immediate data Figure 2.5 Data Transfer Instruction Codes Rev.
Page 84: Arithmetic Operations
Section 2 CPU 2.5.2 Arithmetic Operations Table 2.5 describes the arithmetic instructions. Table 2.5 Arithmetic Instructions Size * Instruction Function Rd ± Rs → Rd, Rd + #IMM → Rd Performs addition or subtraction on data in two general registers, or addition on immediate data and data in a general register.
Page 85: Logic Operations
Section 2 CPU 2.5.3 Logic Operations Table 2.6 describes the four instructions that perform logic operations. Table 2.6 Logic Operation Instructions Size * Instruction Function Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd Performs a logical AND operation on a general register and another general register or immediate data Rd ∨...
Page 86: Shift Operations
Section 2 CPU 2.5.4 Shift Operations Table 2.7 describes the eight shift instructions. Table 2.7 Shift Instructions Size * Instruction Function Rd shift → Rd SHAL SHAR Performs an arithmetic shift operation on general register contents Rd shift → Rd SHLL SHLR Performs a logical shift operation on general register contents...
Page 87 Section 2 CPU Figure 2.6 shows the instruction code format of arithmetic, logic, and shift instructions. ADD, SUB, CMP, ADDX, SUBX (Rm) ADDS, SUBS, INC, DEC, DAA, DAS, NEG, NOT MULXU, DIVXU ADD, ADDX, SUBX, CMP (#XX:8) AND, OR, XOR (Rm) AND, OR, XOR (#xx:8) SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR...
Page 88: Bit Manipulations
Section 2 CPU 2.5.5 Bit Manipulations Table 2.8 describes the bit-manipulation instructions. Figure 2.7 shows their object code formats. Table 2.8 Bit-Manipulation Instructions Size * Instruction Function 1 → (<bit-No.> of <EAd>) BSET Sets a specified bit in a general register or memory to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register.
Page 89 Section 2 CPU Size * Instruction Function C ⊕ (<bit-No.> of <EAd>) → C BXOR XORs the C flag with a specified bit in a general register or memory, and stores the result in the C flag. C ⊕ [~(<bit-No.> of <EAd>)] → C BIXOR XORs the C flag with the inverse of a specified bit in a general register or memory, and stores the result in the C flag.
Page 90 Section 2 CPU BSET, BCLR, BNOT, BTST Operand: register direct (Rn) Bit No.: immediate (#xx:3) Operand: register direct (Rn) Bit No.: register direct (Rm) Operand: register indirect (@Rn) Bit No.: immediate (#xx:3) Operand: register indirect (@Rn) Bit No.: register direct (Rm) Operand: absolute (@aa:8) Bit No.:...
Page 91 Section 2 CPU BIAND, BIOR, BIXOR, BILD, BIST Operand: register direct (Rn) Bit No.: immediate (#xx:3) Operand: register indirect (@Rn) Bit No.: immediate (#xx:3) Operand: absolute (@aa:8) Bit No.: immediate (#xx:3) [Legend] Operation field rm, rn: Register field abs: Absolute address IMM: Immediate data Figure 2.7 Bit Manipulation Instruction Codes (cont)
Page 92: Branching Instructions
Section 2 CPU 2.5.6 Branching Instructions Table 2.9 describes the branching instructions. Figure 2.8 shows their object code formats. Table 2.9 Branching Instructions Instruction Size Function — Branches to the designated address if condition cc is true. The branching conditions are given below. Mnemonic Description Condition...
Page 93 Section 2 CPU disp JMP (@Rm) JMP (@aa:16) JMP (@@aa:8) disp JSR (@Rm) JSR (@aa:16) JSR (@@aa:8) [Legend] Operation field Condition field Register field disp: Displacement abs: Absolute address Figure 2.8 Branching Instruction Codes Rev. 7.00 Mar 10, 2005 page 51 of 652 REJ09B0042-0700...
Page 94: System Control Instructions
Section 2 CPU 2.5.7 System Control Instructions Table 2.10 describes the system control instructions. Figure 2.9 shows their object code formats. Table 2.10 System Control Instructions Size * Instruction Function — Returns from an exception-handling routine SLEEP — Causes a transition from active mode to a power-down mode. See section 5, Power-Down Modes, for details.
Page 95: Block Data Transfer Instruction
Section 2 CPU RTE, SLEEP, NOP LDC, STC (Rn) ANDC, ORC, XORC, LDC (#xx:8) [Legend] Operation field Register field IMM: Immediate data Figure 2.9 System Control Instruction Codes 2.5.8 Block Data Transfer Instruction Table 2.11 describes the block data transfer instruction. Figure 2.10 shows its object code format. Table 2.11 Block Data Transfer Instruction Instruction Size...
Page 96 Section 2 CPU [Legend] Operation field Figure 2.10 Block Data Transfer Instruction Code Rev. 7.00 Mar 10, 2005 page 54 of 652 REJ09B0042-0700...
Page 97: Basic Operational Timing
Section 2 CPU Basic Operational Timing CPU operation is synchronized by a system clock (φ) or a subclock (φ ). For details on these clock signals see section 4, Clock Pulse Generators. The period from a rising edge of φ or φ the next rising edge is called one state.
Page 98: Access To On-Chip Peripheral Modules
Section 2 CPU 2.6.2 Access to On-Chip Peripheral Modules On-chip peripheral modules are accessed in two states or three states. The data bus width is 8 bits, so access is by byte size only. This means that for accessing word data, two instructions must be used.
Page 99: Cpu States
Section 2 CPU Three-state access to on-chip peripheral modules Bus cycle state state state φ or φ Internal Address address bus Internal read signal Internal Read data data bus (read access) Internal write signal Internal data bus Write data (write access) Figure 2.13 On-Chip Peripheral Module Access Cycle (3-State Access) CPU States 2.7.1...
Page 100 Section 2 CPU CPU state Reset state The CPU is initialized Program Active execution state (high speed) mode The CPU executes successive program instructions at high speed, synchronized by the system clock Active (medium speed) mode The CPU executes successive program instructions at reduced speed, synchronized by the system clock...
Page 101: Program Execution State
Section 2 CPU Reset cleared Reset state Exception-handling state Reset occurs Reset Interrupt occurs source Reset Interrupt Exception- occurs occurs source handling occurs complete Program halt state Program execution state SLEEP instruction executed Figure 2.15 State Transitions 2.7.2 Program Execution State In the program execution state the CPU executes program instructions in sequence.
Page 102: Memory Map
Section 2 CPU Memory Map 2.8.1 Memory Map The memory map of the H8/38024, H8/38024S, and H8/38124 are shown in figure 2.16(1), that of the H8/38023, H8/38023S, and H8/38123 in figure 2.16(2), that of the H8/38022, H8/38022S, and H8/38122 in figure 2.16(3), that of the H8/38021, H8/38021S, and H8/38121 in figure 2.16(4), and that of the H8/38020, H8/38020S, and H8/38120 in figure 2.16(5).
Page 103 Section 2 CPU HD64338024 (mask ROM version) HD64F38024, HD64F38024R, HD64F38124 HD64338024S (mask ROM version) HD64338124 (mask ROM version) (flash memory version) HD64738024 (PROM version) H'0000 H'0000 Interrupt vector area Interrupt vector area H'0029 H'0029 H'002A H'002A 32 Kbytes 32 Kbytes On-chip ROM (32768 bytes) (32768 bytes)
Page 104 Section 2 CPU H'0000 Interrupt vector area H'0029 H'002A 24 Kbytes On-chip ROM (24576 bytes) H'5FFF Not used H'F740 LCD RAM (16 bytes) H'F74F Not used H'FB80 On-chip RAM 1024 bytes H'FF7F H'FF80 Internal I/O registers (128 bytes) H'FFFF Figure 2.16(2) H8/38023, H8/38023S, and H8/38123 Memory Map Rev.
Page 105 Section 2 CPU Flash memory version Mask ROM version H'0000 H'0000 Interrupt vector area Interrupt vector area H'0029 H'0029 16 Kbytes H'002A H'002A (16384 bytes) On-chip ROM 16 Kbytes On-chip ROM (16384 bytes) H'3FFF H'3FFF Not used H'7000 Firmware for on-chip emulator H'7FFF Not used Not used...
Page 106 Section 2 CPU H'0000 Interrupt vector area H'0029 H'002A 12 Kbytes On-chip ROM (12288 bytes) H'2FFF Not used H'F740 LCD RAM (16 bytes) H'F74F Not used H'FD80 On-chip RAM 512 bytes H'FF7F H'FF80 Internal I/O registers (128 bytes) H'FFFF Figure 2.16(4) H8/38021, H8/38021S, and H8/38121 Memory Map Rev.
Page 107 Section 2 CPU H'0000 Interrupt vector area H'0029 H'002A 8 Kbytes On-chip ROM (8192 bytes) H'1FFF Not used H'F740 LCD RAM (16 bytes) H'F74F Not used H'FD80 On-chip RAM 512 bytes H'FF7F H'FF80 Internal I/O registers (128 bytes) H'FFFF Figure 2.16(5) H8/38020, H8/38020S, and H8/38120 Memory Map Rev.
Page 108: Application Notes
Section 2 CPU Application Notes 2.9.1 Notes on Data Access 1. Access to Empty Areas: The address space of the H8/300L CPU includes empty areas in addition to the RAM, registers, and ROM areas available to the user. If these empty areas are mistakenly accessed by an application program, the following results will occur.
Page 109 Section 2 CPU Access States Word Byte H'0000 Interrupt vector area (42 bytes) H'0029 H'002A 32 Kbytes On-chip ROM H'7FFF    Not used H'F020 × Internal I/O registers H'F02B    Not used H'F740 LCD RAM (16 bytes) H'F74F ...
Page 110: Notes On Bit Manipulation
Section 2 CPU 2.9.2 Notes on Bit Manipulation The BSET, BCLR, BNOT, BST, and BIST instructions read one byte of data, modify the data, then write the data byte again. Special care is required when using these instructions in cases where two registers are assigned to the same address, in the case of registers that include write- only bits, and when the instruction accesses an I/O port.
Page 111 Section 2 CPU Example 2: BSET instruction executed designating port 3 and P3 are designated as input pins, with a low-level signal input at P3 and a high-level signal at P3 . The remaining pins, P3 to P3 , are output pins and output low-level signals. In this example, the BSET instruction is used to change pin P3 to high-level output.
Page 112 Section 2 CPU To avoid this problem, store a copy of the PDR3 data in a work area in memory. Perform the bit manipulation on the data in the work area, then write this data to PDR3. [A: Prior to executing BSET] The PDR3 value (H'80) is written to a work area in memory MOV.
Page 113 Section 2 CPU 2. Bit manipulation in a register containing a write-only bit Example 3: BCLR instruction executed designating port 3 control register PCR3 As in the examples above, P3 and P3 are input pins, with a low-level signal input at P3 and a high-level signal at P3 .
Page 114 Section 2 CPU To avoid this problem, store a copy of the PCR3 data in a work area in memory. Perform the bit manipulation on the data in the work area, then write this data to PCR3. [A: Prior to executing BCLR] The PCR3 value (H'3F) is written to a work area in memory MOV.
Page 115 Section 2 CPU Table 2.12 Registers with Shared Addresses Register Name Abbreviation Address Timer counter C/Timer load register C TCC/TLC H'FFB5 Port data register 1 * PDR1 H'FFD4 Port data register 3 * PDR3 H'FFD6 Port data register 4 * PDR4 H'FFD7 Port data register 5 *...
Page 116: Notes On Use Of The Eepmov Instruction
Section 2 CPU 2.9.3 Notes on Use of the EEPMOV Instruction • The EEPMOV instruction is a block data transfer instruction. It moves the number of bytes specified by R4L from the address specified by R5 to the address specified by R6. R5 →...
Page 117: Section 3 Exception Handling
Section 3 Exception Handling Section 3 Exception Handling Overview Exception handling is performed in the H8/38024 Group, H8/38024S Group, H8/38024F-ZTAT Group, and H8/38124 Group when a reset or interrupt occurs. Table 3.1 shows the priorities of these two types of exception handling. Table 3.1 Exception Handling Types and Priorities Priority...
Page 118: Interrupt Immediately After Reset
Section 3 Exception Handling When system power is turned on or off, the pin should be held low. R E S Figure 3.1 shows the reset sequence starting from input. R E S See section 14.3.1, Power-On Reset Circuit, for information on the reset sequence for the H8/38124 Group, which is equipped with an on-chip power-on reset circuit.
Page 119: Interrupts
Section 3 Exception Handling Interrupts 3.3.1 Overview The interrupt sources include 13 external interrupts (WKP to WKP , IRQ , IRQ , IRQ , IRQ IRQAEC) and 9 internal interrupts from on-chip peripheral modules. Table 3.2 shows the interrupt sources, their priorities, and their vector addresses. When more than one interrupt is requested, the interrupt with the highest priority is processed.
Page 120 Section 3 Exception Handling Table 3.2 Interrupt Sources and Their Priorities Interrupt Source Interrupt Vector Number Vector Address Priority Reset H'0000 to H'0001 High R E S Watchdog timer H'0008 to H'0009 I R Q Low-voltage detect interrupt * LVDI * H'000A to H'000B I R Q IRQAEC...
Page 121: Interrupt Control Registers
Section 3 Exception Handling 3.3.2 Interrupt Control Registers Table 3.3 lists the registers that control interrupts. Table 3.3 Interrupt Control Registers Name Abbreviation Initial Value Address IRQ edge select register IEGR — H'FFF2 Interrupt enable register 1 IENR1 — H'FFF3 Interrupt enable register 2 IENR2 —...
Page 122 Section 3 Exception Handling Bit 4—IRQ Edge Select (IEG4) Bit 4 selects the input sensing of the pin and pin. I R Q A D T R G Bit 4 IEG4 Description Falling edge of pin input is detected (initial value) I R Q A D T R G Rising edge of...
Page 123 Section 3 Exception Handling Interrupt Enable Register 1 (IENR1)  IENTA IENWP IEN4 IEN3 IENEC2 IEN1 IEN0  Initial value Read/Write IENR1 is an 8-bit read/write register that enables or disables interrupt requests. Bit 7—Timer A Interrupt Enable (IENTA) Bit 7 enables or disables timer A overflow interrupt requests. Bit 7 IENTA Description...
Page 124 Section 3 Exception Handling Bit 2—IRQAEC Interrupt Enable (IENEC2) Bit 2 enables or disables IRQAEC interrupt requests. Bit 2 IENEC2 Description Disables IRQAEC interrupt requests (initial value) Enables IRQAEC interrupt requests Bits 1 and 0—IRQ and IRQ Interrupt Enable (IEN1 and IEN0) Bits 1 and 0 enable or disable IRQ and IRQ interrupt requests.
Page 125 Section 3 Exception Handling Bit 6—A/D Converter Interrupt Enable (IENAD) Bit 6 enables or disables A/D converter interrupt requests. Bit 6 IENAD Description Disables A/D converter interrupt requests (initial value) Enables A/D converter interrupt requests Bit 5—Reserved Bit 5 is reserved bit: it can only be written with 0. Bit 4—Timer G Interrupt Enable (IENTG) Bit 4 enables or disables timer G input capture or overflow interrupt requests.
Page 126 Section 3 Exception Handling Bit 1—Timer C Interrupt Enable (IENTC) Bit 1 enables or disables timer C overflow and underflow interrupt requests. Bit 1 IENTC Description Disables timer C interrupt requests (initial value) Enables timer C interrupt requests Bit 0—Asynchronous Event Counter Interrupt Enable (IENEC) Bit 0 enables or disables asynchronous event counter interrupt requests.
Page 127 Section 3 Exception Handling Bit 7—Timer A Interrupt Request Flag (IRRTA) Bit 7 IRRTA Description Clearing conditions: (initial value) When IRRTA = 1, it is cleared by writing 0 Setting conditions: When the timer A counter value overflows Bit 6—Reserved Bit 6 is reserved;...
Page 128 Section 3 Exception Handling Bits 1 and 0—IRQ and IRQ Interrupt Request Flags (IRRI1 and IRRI0) Bit n IRRIn Description Clearing conditions: (initial value) When IRRIn = 1, it is cleared by writing 0 Setting conditions: When pin is designated for interrupt input and the designated signal edge is I R Q n input (n = 1 or 0)
Page 129 Section 3 Exception Handling Bit 6—A/D Converter Interrupt Request Flag (IRRAD) Bit 6 IRRAD Description Clearing conditions: (initial value) When IRRAD = 1, it is cleared by writing 0 Setting conditions: When A/D conversion is completed and ADSF is cleared to 0 in ADSR Bit 5—Reserved Bit 5 is reserved: it can only be written with 0.
Page 130 Section 3 Exception Handling Bit 2—Timer FL Interrupt Request Flag (IRRTFL) Bit 2 IRRTFL Description Clearing conditions: (initial value) When IRRTFL = 1, it is cleared by writing 0 Setting conditions: When TCFL and OCRFL match in 8-bit timer mode Bit 1—Timer C Interrupt Request Flag (IRRTC) Bit 1 IRRTC...
Page 131 Section 3 Exception Handling Wakeup Interrupt Request Register (IWPR) IWPF7 IWPF6 IWPF5 IWPF4 IWPF3 IWPF2 IWPF1 IWPF0 Initial value R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * Read/Write Note: * Only a write of 0 for flag clearing is possible IWPR is an 8-bit read/write register containing wakeup interrupt request flags.
Page 132: External Interrupts
Section 3 Exception Handling Wakeup Edge Select Register (WEGR) WKEGS7 WKEGS6 WKEGS5 WKEGS4 WKEGS3 WKEGS2 WKEGS1 WKEGS0 Initial value Read/Write WEGR is an 8-bit read/write register that specifies rising or falling edge sensing for pins W K P WEGR is initialized to H'00 by a reset. Bit n—...
Page 133: Internal Interrupts
Section 3 Exception Handling Interrupts IRQ , IRQ , IRQ and IRQ Interrupts IRQ4, IRQ3, IRQ1, and IRQ0 are requested by input signals to pins I R Q I R Q I R Q . These interrupts are detected by either rising edge sensing or falling edge sensing, I R Q depending on the settings of bits IEG4, IEG3, IEG1, and IEG0 in IEGR.
Page 134: Interrupt Operations
Section 3 Exception Handling 3.3.5 Interrupt Operations Interrupts are controlled by an interrupt controller. Figure 3.2 shows a block diagram of the interrupt controller. Figure 3.3 shows the flow up to interrupt acceptance. Interrupt controller External or internal interrupts Interrupt request External interrupts or...
Page 135 Section 3 Exception Handling • If the interrupt request is accepted, after processing of the current instruction is completed, both PC and CCR are pushed onto the stack. The state of the stack at this time is shown in figure 3.4. The PC value pushed onto the stack is the address of the first instruction to be executed upon return from interrupt handling.
Page 136 Section 3 Exception Handling Program execution state IRRI0 = 1 IEN0 = 1 IRRI1 = 1 IEN1 = 1 IRREC2 = 1 IENEC2 = 1 IRRDT = 1 IENDT = 1 I = 0 PC contents saved CCR contents saved I ←...
Page 137 Section 3 Exception Handling SP − 4 SP (R7) SP − 3 SP + 1 SP − 2 SP + 2 SP − 1 SP + 3 SP (R7) SP + 4 Even address Stack area Prior to start of interrupt After completion of interrupt PC and CCR exception handling...
Page 138 Section 3 Exception Handling Figure 3.5 Interrupt Sequence Rev. 7.00 Mar 10, 2005 page 96 of 652 REJ09B0042-0700...
Page 139: Interrupt Response Time
Section 3 Exception Handling 3.3.6 Interrupt Response Time Table 3.4 shows the number of wait states after an interrupt request flag is set until the first instruction of the interrupt handler is executed. Table 3.4 Interrupt Wait States Item States Total Waiting time for completion of executing instruction * 1 to 13...
Page 140: Application Notes
Section 3 Exception Handling Application Notes 3.4.1 Notes on Stack Area Use When word data is accessed in the LSI, the least significant bit of the address is regarded as 0. Access to the stack always takes place in word size, so the stack pointer (SP: R7) should never indicate an odd address.
Page 141: Notes On Rewriting Port Mode Registers
Section 3 Exception Handling 3.4.2 Notes on Rewriting Port Mode Registers When a port mode register is rewritten to switch the functions of external interrupt pins and when the value of ECPWME in AEGSR is rewritten to switch between selection/non-selection of IRQAEC, the following points should be observed.
Page 142 Section 3 Exception Handling Interrupt Request Flags Set to 1 Conditions IWPR IWPF7 When PMR5 bit WKP7 is changed from 0 to 1 while pin is low and WEGR bit W K P WKEGS7 = 0. When PMR5 bit WKP7 is changed from 1 to 0 while pin is low and WEGR bit W K P WKEGS7 = 1.
Page 143: Method For Clearing Interrupt Request Flags
Section 3 Exception Handling executed immediately after the port mode register (or AEGSR) access without executing an intervening instruction, the flag will not be cleared. An alternative method is to avoid the setting of interrupt request flags when pin functions are switched by keeping the pins at the high level so that the conditions in table 3.5 do not occur.
Page 144 Section 3 Exception Handling • Example of a malfunction When flags are cleared with multiple instructions, other flags might be cleared during execution of the instructions, even though they are currently set, and this will cause a malfunction. Here is an example in which IRRI0 is cleared and disabled in the process of clearing IRRI1 (bit 1 of IRR1).
Page 145: Section 4 Clock Pulse Generators
Section 4 Clock Pulse Generators Section 4 Clock Pulse Generators Overview Clock oscillator circuitry (CPG: clock pulse generator) is provided on-chip, including both a system clock pulse generator and a subclock pulse generator. The system clock pulse generator consists of a system clock oscillator and system clock dividers. The subclock pulse generator consists of a subclock oscillator circuit and a subclock divider.
Page 146: System Clock And Subclock
Section 4 Clock Pulse Generators Internal reset signal (other than watchdog timer or low-voltage detect circuit reset) IRQAEC Latch φ System System φ clock φ clock φ System divider oscillator φ clock (1/2) φ /2 φ divider Prescaler S φ /128 (13 bits) φ...
Page 147: Register Descriptions
Section 4 Clock Pulse Generators 4.1.3 Register Descriptions Table 4.1 lists the registers that control the clock pulse generators. The registers listed in table 4.1 are only implemented in the H8/38124 Group. Table 4.1 Clock Pulse Generator Control Registers Name Abbreviation Initial Value Address...
Page 148: System Clock Generator
Section 4 Clock Pulse Generators Bit 2—IRQAEC Flag (IRQAECF) This bit indicates the IRQAEC pin input level set during resets. Bit 2 IRQAECF Description IRQAEC pin set to GND during resets IRQAEC pin set to V during resets Bit 1—OSC Flag (OSCF) This bit indicates the oscillator operating with the system clock pulse generator.
Page 149 Section 4 Clock Pulse Generators Ω ±20% R = 1 M Crystal Frequency Recommendation oscillator value 12 pF ±20% 4.19 MHz Note: Circuit constants should be determined in consultation with the resonator manufacturer. Figure 4.3(1) Typical Connection to Crystal Oscillator (H8/38024, H8/38024R Group) Ω...
Page 150 Section 4 Clock Pulse Generators Table 4.2 Crystal Oscillator Parameters Frequency (MHz) 4.193 RS max (Ω) max (pF) Connecting a Ceramic Oscillator Figure 4.5(1) shows a typical method of connecting a ceramic oscillator to the H8/38024 or H8/38024R Group, and figure 4.5(2) shows a typical method of connecting a crystal oscillator to the H8/38024S and H8/38124 Group.
Page 151 Section 4 Clock Pulse Generators Notes on Board Design When generating clock pulses by connecting a crystal or ceramic oscillator, pay careful attention to the following points. Avoid running signal lines close to the oscillator circuit, since the oscillator may be adversely affected by induction currents.
Page 152 Section 4 Clock Pulse Generators External Clock Input Method Connect an external clock signal to pin OSC , and leave pin OSC open. Figure 4.7 shows a typical connection. External clock input Open Figure 4.7 External Clock Input (Example) Oscillator Clock (φ φ φ φ Frequency Duty cycle 45% to 55%...
Page 153: Subclock Generator
Section 4 Clock Pulse Generators Subclock Generator Connecting a 32.768 kHz/38.4 kHz Crystal Oscillator Clock pulses can be supplied to the subclock divider by connecting a 32.768 kHz/38.4 kHz crystal oscillator, as shown in figure 4.8. Follow the same precautions as noted under 3. notes on board design for the system clock in section 4.2.
Page 154 Section 4 Clock Pulse Generators Open Figure 4.10 Pin Connection when not Using Subclock External Clock Input Connect the external clock to the X1 pin and leave the X2 pin open, as shown in figure 4.11. Note that no external clock should be input to the H8/38124 Group. External clock input Open Figure 4.11 Pin Connection when Inputting External Clock...
Page 155: Prescalers
Section 4 Clock Pulse Generators Prescalers The H8/38024 Group is equipped with two on-chip prescalers having different input clocks (prescaler S and prescaler W). Prescaler S is a 13-bit counter using the system clock (φ) as its input clock. Its prescaled outputs provide internal clock signals for on-chip peripheral modules. Prescaler W is a 5-bit counter using a 32.768 kHz or 38.4 kHz signal divided by 4 (φ...
Page 156: Note On Oscillators
Section 4 Clock Pulse Generators Note on Oscillators Oscillator characteristics are closely related to board design and should be carefully evaluated by the user in mask ROM and ZTAT versions, referring to the examples shown in this section. Oscillator circuit constants will differ depending on the oscillator element, stray capacitance in its interconnecting circuit, and other factors.
Page 157: Definition Of Oscillation Stabilization Wait Time
Section 4 Clock Pulse Generators Modification point OSC1 OSC1 OSC2 OSC2 Negative resistance, addition of −R (1) Negative Resistance Measuring Circuit (2) Oscillator Circuit Modification Suggestion 1 Modification point Modification point OSC1 OSC1 OSC2 OSC2 (3) Oscillator Circuit Modification Suggestion 2 (4) Oscillator Circuit Modification Suggestion 3 Figure 4.13 Negative Resistance Measurement and Circuit Modification Suggestions 4.5.1...
Page 158 Section 4 Clock Pulse Generators 1. Oscillation stabilization time (t The time from the point at which the system clock oscillator oscillation waveform starts to change when an interrupt is generated, until the amplitude of the oscillation waveform increases and the oscillation frequency stabilizes.
Page 159: Notes On Use Of Crystal Oscillator Element (Excluding Ceramic Oscillator Element)
Section 4 Clock Pulse Generators amplitude of the oscillation waveform increases and the oscillation frequency stabilizes—that is, the oscillation stabilization time—is required. The oscillation stabilization time in the case of these state transitions is the same as the oscillation stabilization time at power-on (the time from the point at which the power supply voltage reaches the prescribed level until the oscillation stabilizes), specified by "oscillation stabilization time t rc "...
Page 160: Note On Use Of Hd64F38024
Section 4 Clock Pulse Generators For example, if erroneous operation occurs with a wait time setting of 16 states, check the operation with a wait time setting of 1,024 * states or more. If the same kind of erroneous operation occurs after a reset as after a state transition, hold the R E S pin low for a longer period.
Page 161: Section 5 Power-Down Modes
Section 5 Power-Down Modes Section 5 Power-Down Modes Overview The LSI has nine modes of operation after a reset. These include eight power-down modes, in which power dissipation is significantly reduced. Table 5.1 gives a summary of the nine operating modes.
Page 162 Section 5 Power-Down Modes Program Program Reset state execution state halt state SLEEP instruction Active Sleep (high-speed) (high-speed) Program mode mode halt state Standby mode SLEEP instruction Active Sleep (medium-speed) (medium-speed) mode mode SLEEP SLEEP instruction instruction Watch Subactive Subsleep mode mode mode...
Page 163 Section 5 Power-Down Modes Table 5.2 Internal State in Each Operating Mode Active Mode Sleep Mode High- Medium- High- Medium- Watch Subactive Subsleep Standby Function Speed Speed Speed Speed Mode Mode Mode Mode System clock oscillator Functions Functions Functions Functions Halted Halted Halted Halted...
Page 164: System Control Registers
Section 5 Power-Down Modes 11. On the H8/38124 Group, operates only when the on-chip oscillator is selected; otherwise stops and stands by. On the H8/38024, H8/38024S, and H8/38024R Group, stops and stands by. 5.1.1 System Control Registers The operation mode is selected using the system control registers described in table 5.3. Table 5.3 System Control Registers Name...
Page 165 Section 5 Power-Down Modes Bits 6 to 4—Standby Timer Select 2 to 0 (STS2 to STS0) These bits designate the time the CPU and peripheral modules wait for stable clock operation after exiting from standby mode or watch mode to active mode due to an interrupt. The designation should be made according to the operating frequency so that the waiting time is at least equal to the oscillation stabilization time.
Page 166 Section 5 Power-Down Modes Bit 3—Low Speed on Flag (LSON) This bit chooses the system clock (φ) or subclock (φ ) as the CPU operating clock when watch mode is cleared. The resulting operation mode depends on the combination of other control bits and interrupt input.
Page 167 Section 5 Power-Down Modes Bit 4—Noise Elimination Sampling Frequency Select (NESEL) This bit selects the frequency at which the watch clock signal (φ ) generated by the subclock pulse generator is sampled, in relation to the oscillator clock (φ ) generated by the system clock pulse generator.
Page 168: Sleep Mode
Section 5 Power-Down Modes Bit 2 MSON Description Operation in active (high-speed) mode (initial value) Operation in active (medium-speed) mode Bits 1 and 0—Subactive Mode Clock Select (SA1, SA0) /2, φ /4, or φ These bits select the CPU clock rate (φ /8) in subactive mode.
Page 169: Clearing Sleep Mode
Section 5 Power-Down Modes 5.2.2 Clearing Sleep Mode Sleep mode is cleared by any interrupt (timer A, timer C, timer F, timer G, asynchronous event counter, IRQAEC, IRQ , IRQ , IRQ , IRQ , WKP to WKP , SCI3, A/D converter), or by input at pin.
Page 170: Standby Mode
Section 5 Power-Down Modes Standby Mode 5.3.1 Transition to Standby Mode The system goes from active mode to standby mode when a SLEEP instruction is executed while the SSBY bit in SYSCR1 is set to 1, the LSON bit in SYSCR1 is cleared to 0, and bit TMA3 in TMA is cleared to 0.
Page 171 Section 5 Power-Down Modes • When a oscillator is used The table below gives settings for various operating frequencies. Set bits STS2 to STS0 for a wait time at least as long as the oscillation stabilization time. Table 5.4(1) Clock Frequency and Stabilization Time (H8/38024, H8/38024S, H8/38024R Group) (Unit: ms) STS2...
Page 172: Standby Mode Transition And Pin States
Section 5 Power-Down Modes • When the on-chip oscillator is used 8,192 states (STS2 = STS1 = STS0 = 0) is recommended if the on-chip oscillator is used on the H8/38124 Group. 5.3.4 Standby Mode Transition and Pin States When a SLEEP instruction is executed in active (high-speed) mode or active (medium-speed) mode while bit SSBY is set to 1 and bit LSON is cleared to 0 in SYSCR1, and bit TMA3 is cleared to 0 in TMA, a transition is made to standby mode.
Page 173: Notes On External Input Signal Changes Before/After Standby Mode
Section 5 Power-Down Modes 5.3.5 Notes on External Input Signal Changes before/after Standby Mode 1. When external input signal changes before/after standby mode or watch mode When an external input signal such as , or IRQAEC is input, both the high- and I R Q W K P low-level widths of the signal must be at least two cycles of system clock φ...
Page 174: Watch Mode
Section 5 Power-Down Modes Active (high-speed, Wait for Active (high-speed, Operating medium-speed) mode Standby mode oscillation medium-speed) mode mode or subactive mode or watch mode to settle or subactive mode subcyc subcyc subcyc subcyc φ or φ External input signal Capture possible: case 1 Capture possible:...
Page 175: Clearing Watch Mode
Section 5 Power-Down Modes 5.4.2 Clearing Watch Mode Watch mode is cleared by an interrupt (timer A, timer F, timer G, IRQ0, or WKP7 to WKP0) or by input at the pin. R E S • Clearing by interrupt When watch mode is cleared by interrupt, the mode to which a transition is made depends on the settings of LSON in SYSCR1 and MSON in SYSCR2.
Page 176: Subsleep Mode
Section 5 Power-Down Modes Subsleep Mode 5.5.1 Transition to Subsleep Mode The system goes from subactive mode to subsleep mode when a SLEEP instruction is executed while the SSBY bit in SYSCR1 is cleared to 0, LSON bit in SYSCR1 is set to 1, and TMA3 bit in TMA is set to 1.
Page 177: Subactive Mode
Section 5 Power-Down Modes Subactive Mode 5.6.1 Transition to Subactive Mode Subactive mode is entered from watch mode if a timer A, timer F, timer G, IRQ , or WKP interrupt is requested while the LSON bit in SYSCR1 is set to 1. From subsleep mode, subactive mode is entered if a timer A, timer C, timer F, timer G, asynchronous event counter, SCI3, IRQAEC, IRQ , IRQ...
Page 178: Active (Medium-Speed) Mode
Section 5 Power-Down Modes Active (Medium-Speed) Mode 5.7.1 Transition to Active (Medium-Speed) Mode If the MSON bit in SYSCR2 is set to 1 while the LSON bit in SYSCR1 is cleared to 0, a transition to active (medium-speed) mode results from IRQ , IRQ or WKP to WKP...
Page 179: Direct Transfer
Section 5 Power-Down Modes Direct Transfer 5.8.1 Overview of Direct Transfer The CPU can execute programs in three modes: active (high-speed) mode, active (medium-speed) mode, and subactive mode. A direct transfer is a transition among these three modes without the stopping of program execution.
Page 180: Direct Transition Times
Section 5 Power-Down Modes • Direct transfer from active (medium-speed) mode to subactive mode When a SLEEP instruction is executed in active (medium-speed) mode while the SSBY and LSON bits in SYSCR1 are set to 1, the DTON bit in SYSCR2 is set to 1, and the TMA3 bit in TMA is set to 1, a transition is made to subactive mode via watch mode.
Page 181 Section 5 Power-Down Modes 2. Time for direct transition from active (medium-speed) mode to active (high-speed) mode A direct transition from active (medium-speed) mode to active (high-speed) mode is performed by executing a SLEEP instruction in active (medium-speed) mode while bits SSBY and LSON are both cleared to 0 in SYSCR1, and bit MSON is cleared to 0 and bit DTON is set to 1 in SYSCR2.
Page 182: Notes On External Input Signal Changes Before/After Direct Transition
Section 5 Power-Down Modes 4. Time for direct transition from subactive mode to active (medium-speed) mode A direct transition from subactive mode to active (medium-speed) mode is performed by executing a SLEEP instruction in subactive mode while bit SSBY is set to 1 and bit LSON is cleared to 0 in SYSCR1, bits MSON and DTON are both set to 1 in SYSCR2, and bit TMA3 is set to 1 in TMA.
Page 183: Module Standby Mode
Section 5 Power-Down Modes Module Standby Mode 5.9.1 Setting Module Standby Mode Module standby mode is set for individual peripheral functions. All the on-chip peripheral modules can be placed in module standby mode. When a module enters module standby mode, the system clock supply to the module is stopped and operation of the module halts.
Page 184 Section 5 Power-Down Modes Register Name Bit Name Operation CKSTPR2 LDCKSTP LCD module standby mode is cleared LCD is set to module standby mode PW1CKSTP PWM1 module standby mode is cleared PWM1 is set to module standby mode WDCKSTP Watchdog timer module standby mode is cleared Watchdog timer is set to module standby mode AECKSTP Asynchronous event counter module standby mode...
Page 185: Section 6 Rom
Section 6 ROM Section 6 ROM Overview The H8/38024, H8/38024S, and H8/38124 have 32 Kbytes of on-chip mask ROM, the H8/38023, H8/38023S, and H8/38123 have 24 Kbytes, the H8/38022, H8/38022S, and H8/38122 have 16 Kbytes, the H8/38021, H8/38021S, and H8/38121 have 12 Kbytes, and the H8/38020, H8/38020S, and H8/38120 have 8 Kbytes.
Page 186: H8/38024 Prom Mode
Section 6 ROM H8/38024 PROM Mode 6.2.1 Setting to PROM Mode If the on-chip ROM is PROM, setting the chip to PROM mode stops operation as a microcontroller and allows the PROM to be programmed in the same way as the standard HN27C101 EPROM.
Page 187 Section 6 ROM H8/38024 EPROM socket FP-80A, TFP-80C FP-80B HN27C101 (32-pin) TEST = AV Note: Pins not indicated in the figure should be left open. Figure 6.2 Socket Adapter Pin Correspondence (with HN27C101) Rev. 7.00 Mar 10, 2005 page 145 of 652 REJ09B0042-0700...
Page 188 Section 6 ROM Address in Address in MCU mode PROM mode H'0000 H'0000 On-chip PROM H'7FFF H'7FFF Uninstalled area * H'1FFFF Note: * The output data is not guaranteed if this address area is read in PROM mode. Therefore, when programming with a PROM programmer, be sure to specify addresses from H'0000 to H'7FFF.
Page 189: H8/38024 Programming
Section 6 ROM H8/38024 Programming The write, verify, and other modes are selected as shown in table 6.2 in H8/38024 PROM mode. Table 6.2 Mode Selection in PROM Mode (H8/38024) Pins Mode to EO to EA P G M Write Data input Address input Verify...
Page 190 Section 6 ROM Start Set write/verify mode = 6.0 V ± 0.25 V, V = 12.5 V ± 0.3 V Address = 0 n = 0 → n + 1 n < 25 = 0.2 ms ± 5% Write time t →...
Page 191 Section 6 ROM Tables 6.3 and 6.4 give the electrical characteristics in programming mode. Table 6.3 DC Characteristics Conditions: V = 6.0 V ±0.25 V, V = 12.5 V ±0.3 V, V = 0 V, T = 25°C ±5°C Test Item Symbol Min Unit...
Page 192 Section 6 ROM Table 6.4 AC Characteristics Conditions: V = 6.0 V ±0.25 V, V = 12.5 V ±0.3 V, T = 25°C ±5°C Item Symbol Unit Test Condition Figure 6.5 * Address setup time — — µs setup time —...
Page 193 Section 6 ROM Figure 6.5 shows a PROM write/verify timing diagram. Write Verify Address Data Input data Output data CC +1 Note: * t is defined by the value shown in figure 6.4, High-Speed, High-Reliability Programming Flowchart. Figure 6.5 PROM Write/Verify Timing Rev.
Page 194: Programming Precautions
) is 12.5 V. Use of a higher voltage can permanently damage the chip. Be especially careful with respect to PROM programmer overshoot. Setting the PROM programmer to Renesas (former Hitachi) specifications for the HN27C101 will result in correct V of 12.5 V.
Page 195: Reliability Of Programmed Data
If a series of programming errors occurs while the same PROM programmer is in use, stop programming and check the PROM programmer and socket adapter for defects. Please inform Renesas Technology of any abnormal conditions noted during or after programming or in screening of program data after high-temperature baking.
Page 196: Flash Memory Overview
Section 6 ROM Flash Memory Overview 6.5.1 Features The features of the 32-Kbyte or 16-Kbyte flash memory built into the flash memory versions are summarized below. • Programming/erase methods  The flash memory is programmed 128 bytes at a time. Erase is performed in single-block units.
Page 197: Block Diagram
Section 6 ROM 6.5.2 Block Diagram Internal address bus Internal data bus (16 bits) FLMCR1 TES pin FLMCR2 Operating Bus interface/controller P95 pin mode P34 pin FLPWCR FENR Flash memory [Legend] FLMCR1: Flash memory control register 1 FLMCR2: Flash memory control register 2 EBR: Erase block register FLPWCR: Flash memory power control register...
Page 198: Block Configuration
Section 6 ROM 6.5.3 Block Configuration Figure 6.8 shows the block configuration of the flash memory. The thick lines indicate erasing units, the narrow lines indicate programming units, and the values are addresses. In versions with 32 Kbytes of flash memory, the flash memory is divided into 1 Kbyte × 4 blocks and 28 Kbytes × 1 block.
Page 199 Section 6 ROM H'0000 H'0001 H'0002 Programming unit: 128 bytes H'007F Erase unit H'0080 H'0081 H'0082 H'00FF 1 Kbyte H'0380 H'0381 H'0382 H'03FF H'0400 H'0401 H'0402 Programming unit: 128 bytes H'047F Erase unit H'0480 H'0481 H'0482 H'04FF 1 Kbyte H'0780 H'0781 H'0782 H'07FF...
Page 200: Register Configuration
Section 6 ROM 6.5.4 Register Configuration Table 6.5 lists the register configuration to control the flash memory when the built in flash memory is effective. Table 6.5 Register Configuration Register Name Abbreviation Initial Value Address Flash memory control register 1 FLMCR1 H'00 H'F020...
Page 201 Section 6 ROM Bit 6—Software Write Enable (SWE) This bit is to set enabling/disabling of programming/enabling of flash memory (set when bits 5 to 0 and the EBR register are to be set). Bit 6 Description Programming/erasing is disabled. Other FLMCR1 register bits and all EBR bits cannot be set.
Page 202 Section 6 ROM Bit 3 Description Erase-verify mode is cancelled (initial value) The flash memory changes to erase-verify mode Bit 2—Program-Verify (PV) This bit is to set changing to or cancelling program-verify mode (do not set SWE, ESU, PSU, EV, E, and P bits at the same time).
Page 203: Flash Memory Control Register 2 (Flmcr2)
Section 6 ROM 6.6.2 Flash Memory Control Register 2 (FLMCR2) FLER — — — — — — — Initial value Read/Write — — — — — — — FLMCR2 is a register that displays the state of flash memory programming/erasing. FLMCR2 is a read-only register, and should not be written to.
Page 204: Erase Block Register (Ebr)
Section 6 ROM 6.6.3 Erase Block Register (EBR) — — — Initial value Read/Write — — — EBR specifies the flash memory erase area block. EBR is initialized to H'00 when the SWE bit in FLMCR1 is 0. Do not set more than one bit at a time, as this will cause all the bits in EBR to be automatically cleared to 0.
Page 205: Flash Memory Enable Register (Fenr)
Section 6 ROM Bit 7—Power-down Disable (PDWND) This bit selects the power-down mode of the flash memory when a transition to the subactive mode is made. Bit 7 PDWND Description When this bit is 0 and a transition is made to the subactive mode, the flash memory enters the power-down mode.
Page 206: On-Board Programming Modes
Section 6 ROM On-Board Programming Modes There are two modes for programming/erasing of the flash memory; boot mode, which enables on- board programming/erasing, and programmer mode, in which programming/erasing is performed with a PROM programmer. On-board programming/erasing can also be performed in user program mode.
Page 207 Section 6 ROM 3. When the boot program is initiated, the chip measures the low-level period of asynchronous SCI communication data (H'00) transmitted continuously from the host. The chip then calculates the bit rate of transmission from the host, and adjusts the SCI3 bit rate to match that of the host.
Page 208 Section 6 ROM Table 6.8 Boot Mode Operation Host Operation LSI Operation Processing Contents Processing Contents Item Branches to boot program at reset-start. Bit rate Continuously transmits data H'00 at · Measures low-level period of receive data H'00. adjustment specified bit rate. ·...
Page 209: Programming/Erasing In User Program Mode
Section 6 ROM 6.7.2 Programming/Erasing in User Program Mode The term user mode refers to the status when a user program is being executed. On-board programming/erasing of an individual flash memory block can also be performed in user program mode by branching to a user program/erase control program. The user must set branching conditions and provide on-board means of supplying programming data.
Page 210: Notes On On-Board Programming
Section 6 ROM 6.7.3 Notes on On-Board Programming 1. You must use the system clock oscillator when programming or erasing flash memory on the H8/38124 Group. The on-chip oscillator should not be used for programming or erasing flash memory. See section 4.2, On-Chip Oscillator Selection Method, for information on switching between the system clock oscillator and the on-chip oscillator.
Page 211 Section 6 ROM reprogramming data computation according to table 6.10, and additional programming data computation according to table 6.11. 4. Consecutively transfer 128 bytes of data in byte units from the reprogramming data area or additional-programming data area to the flash memory. The program address and 128-byte data are latched in the flash memory.
Page 212 Section 6 ROM Write pulse application subroutine Apply Write Pulse START Set SWE bit in FLMCR1 WDT enable Wait 1 µs Set PSU bit in FLMCR1 Store 128-byte program data in program data area and reprogram data area Wait 50 µs n = 1 Set P bit in FLMCR1 m = 0...
Page 213 Section 6 ROM Table 6.10 Reprogram Data Computation Table Program Data Verify Data Reprogram Data Comments Programming completed Reprogram bit — Remains in erased state Table 6.11 Additional-Program Data Computation Table Additional-Program Reprogram Data Verify Data Data Comments Additional-program bit No additional programming No additional programming No additional programming...
Page 214: Erase/Erase-Verify
Section 6 ROM 6.8.2 Erase/Erase-Verify When erasing flash memory, the erase/erase-verify flowchart shown in figure 6.11 should be followed. 1. Prewriting (setting erase block data to all 0s) is not necessary. 2. Erasing is performed in block units. Make only a single-bit specification in the erase block register (EBR).
Page 215 Section 6 ROM Erase start SWE bit ← 1 Wait 1 µs n ← 1 Set EBR Enable WDT ESU bit ← 1 Wait 100 µs E bit ← 1 Wait 10 ms E bit ← 0 Wait 10 µs ESU bit ←...
Page 216: Program/Erase Protection
Section 6 ROM Program/Erase Protection There are three kinds of flash memory program/erase protection; hardware protection, software protection, and error protection. 6.9.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted because of a transition to reset, subactive mode, subsleep mode, watch mode, or standby mode.
Page 217: Error Protection
Use a PROM programmer that supports the MCU device type with the on-chip Renesas Technology (former Hitachi Ltd.) 64-Kbyte flash memory (F-ZTAT64V3). A 10-MHz input clock is required. For the conditions for transition to programmer mode, see table 6.7.
Page 218: Programmer Mode Commands
Section 6 ROM 6.10.2 Programmer Mode Commands The following commands are supported in programmer mode. • Memory Read Mode • Auto-Program Mode • Auto-Erase Mode • Status Read Mode Status polling is used for auto-programming, auto-erasing, and status read modes. In status read mode, detailed internal information is output after the execution of auto-programming or auto- erasing.
Page 219 Section 6 ROM HD64F38024, HD64F38024R Socket Adapter HN28F101 (32 Pins) Pin No. (Conversion to Pin Name 32-Pin FP-80A Pin Name Pin No. FP-80B Arrangement) TFP-80C I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 AVcc TEST [Legend] FWE: Flash-write enable I/O7 to I/O0: Data input/output A16 to A0: Address input Chip enable...
Page 220 Section 6 ROM HD64F38124, HD64F38122 Socket Adapter (Conversion to HN28F101 (32 Pins) Pin No. 32-Pin Pin Name FP-80A Arrangement) Pin Name Pin No. TFP-80C I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 AVcc TEST [Legend] FWE: Flash-write enable I/O7 to I/O0: Data input/output A16 to A0: Address input Chip enable...
Page 221: Memory Read Mode
Section 6 ROM 6.10.3 Memory Read Mode 1. After completion of auto-program/auto-erase/status read operations, a transition is made to the command wait state. When reading memory contents, a transition to memory read mode must first be made with a command write, after which the memory contents are read. Once memory read mode has been entered, consecutive reads can be performed.
Page 222 Section 6 ROM Table 6.15 AC Characteristics in Transition from Memory Read Mode to Another Mode Conditions: V = 3.3 V ±0.3 V, V = 0 V, T = 25°C ±5°C Item Symbol Unit Notes Command write cycle — µs Figure 6.14 nxtc hold time...
Page 223 Section 6 ROM Table 6.16 AC Characteristics in Memory Read Mode Conditions: V = 3.3 V ±0.3 V, V = 0 V, T = 25°C ±5°C Item Symbol Unit Notes Access time — µs Figure 6.15 output delay time — Figure 6.16 output delay time —...
Page 224: Auto-Program Mode
Section 6 ROM 6.10.4 Auto-Program Mode 1. When reprogramming previously programmed addresses, perform auto-erasing before auto- programming. 2. Perform auto-programming once only on the same address block. It is not possible to program an address block that has already been programmed. 3.
Page 225 Section 6 ROM Table 6.17 AC Characteristics in Auto-Program Mode Conditions: V = 3.3 V ±0.3 V, V = 0 V, T = 25°C ±5°C Item Symbol Unit Notes Command write cycle — µs Figure 6.17 nxtc hold time — setup time —...
Page 226: Auto-Erase Mode
Section 6 ROM 6.10.5 Auto-Erase Mode 1. Auto-erase mode supports only entire memory erasing. 2. Do not perform a command write during auto-erasing. 3. Confirm normal end of auto-erasing by checking I/O6. Alternatively, status read mode can also be used for this purpose (I/O7 status polling uses the auto-erase operation end decision pin). 4.
Page 227: Status Read Mode
Section 6 ROM A15−A0 nxtc nxtc ests erase I/O7 Erase end decision signal I/O6 Erase normal decision signal I/O5−I/O0 H'20 H'20 H'00 Figure 6.18 Auto-Erase Mode Timing Waveforms 6.10.6 Status Read Mode 1. Status read mode is provided to identify the kind of abnormal end. Use this mode when an abnormal end occurs in auto-program mode or auto-erase mode.
Page 228 Section 6 ROM Table 6.19 AC Characteristics in Status Read Mode Conditions: V = 3.3 V ±0.3 V, V = 0 V, T = 25°C ±5°C Item Symbol Unit Notes Read time after command write — µs Figure 6.19 nxtc hold time —...
Page 229: Status Polling
Section 6 ROM Table 6.20 Status Read Mode Return Codes Pin Name Initial Value Indications I/O7 1: Abnormal end 0: Normal end I/O6 1: Command error 0: Otherwise I/O5 1: Programming error 0: Otherwise I/O4 1: Erasing error 0: Otherwise ...
Page 230: Programmer Mode Transition Time
2. The flash memory is initially in the erased state when the device is shipped by Renesas Technology. For other chips for which the erasure history is unknown, it is recommended that auto-erasing be executed to check and supplement the initialization (erase) level.
Page 231: Power-Down States For Flash Memory
Section 6 ROM 6.11 Power-Down States for Flash Memory In user mode, the flash memory will operate in either of the following states: • Normal operating mode The flash memory can be read and written to at high speed. • Power-down operating mode The power supply circuit of the flash memory is partly halted and can be read under low power consumption.
Page 232 Section 6 ROM Rev. 7.00 Mar 10, 2005 page 190 of 652 REJ09B0042-0700...
Page 233: Section 7 Ram
Section 7 RAM Section 7 RAM Overview The H8/38024, H8/38023, H8/38022, H8/38124, H8/38123, H8/38122, H8/38024S, H8/38023S, and H8/38022S have 1 Kbyte of high-speed static RAM on-chip, and the H8/38021, H8/38020, H8/38121, H8/38120, H8/38021S, and H8/38020S have 512 bytes. The RAM is connected to the CPU by a 16-bit data bus, allowing high-speed 2-state access for both byte data and word data.
Page 234 Section 7 RAM Rev. 7.00 Mar 10, 2005 page 192 of 652 REJ09B0042-0700...
Page 235: Section 8 I/O Ports
Section 8 I/O Ports Section 8 I/O Ports Overview The LSI is provided with five 8-bit I/O ports, two 4-bit I/O ports, one 3-bit I/O port, one 8-bit input-only port, one 1-bit input-only port, and one 6-bit output-only port. Table 8.1 indicates the functions of each port.
Page 236 Section 8 I/O Ports Function Switching Port Description Pins Other Functions Registers • Port 4 External interrupt 0 PMR2 1-bit input port I R Q • /TXD SCI3 data output (TXD SCR3 3-bit I/O port /RXD data input (RXD ), clock SMR3 /SCK input/output (SCK...
Page 237: Port 1
Section 8 I/O Ports Port 1 8.2.1 Overview Port 1 is a 4-bit I/O port. Figure 8.1 shows its pin configuration. /IRQ /TMIF Port 1 /IRQ /ADTRG /TMIG Note: * Pin 16 and the associated function are not implemented on the H8/38124 Group. Figure 8.1 Port 1 Pin Configuration 8.2.2 Register Configuration and Description...
Page 238 Section 8 I/O Ports Port Data Register 1 (PDR1) — — — — Initial value — — — — Read/Write — — — — PDR1 is an 8-bit register that stores data for port 1 pins P1 , P1 *, P1 , and P1 .
Page 239 Section 8 I/O Ports Port Pull-Up Control Register 1 (PUCR1) PUCR1 PUCR1 — PUCR1 PUCR1 — — — Initial value — — — — Read/Write PUCR1 controls whether the MOS pull-up of each of the port 1 pins P1 , P1 *, P1 , and P1 is on...
Page 240 Section 8 I/O Ports Bit 4—P1 Pin Function Switch (IRQ4) I R Q A D T R G This bit selects whether pin P1 is used as P1 or as I R Q A D T R G I R Q A D T R G Bit 4 IRQ4...
Page 241 Section 8 I/O Ports This section only deals with the bits related to timer G and the watchdog timer. For the functions of the bits, see the descriptions of port 3 (POF1) and port 4 (IRQ0). Bit 2—Watchdog Timer Source Clock (WDCKS) This bit selects the watchdog timer source clock.
Page 242: Pin Functions
Section 8 I/O Ports 8.2.3 Pin Functions Table 8.3 shows the port 1 pin functions. Table 8.3 Port 1 Pin Functions Pin Functions and Selection Method /TMIF The pin function depends on bit IRQ3 in PMR1, bits CKSL2 to CKSL0 in TCRF, I R Q and bit PCR1 in PCR1.
Page 243: Pin States
Section 8 I/O Ports 8.2.4 Pin States Table 8.4 shows the port 1 pin states in each operating mode. Table 8.4 Port 1 Pin States Pins Reset Sleep Subsleep Standby Watch Subactive Active Functional Functional /TMIF High- Retains Retains High- Retains I R Q impedance *...
Page 244: Port 3
Section 8 I/O Ports Port 3 8.3.1 Overview Port 3 is an 8-bit I/O port, configured as shown in figure 8.2. P3 /AEVL P3 /AEVH Port 3 P3 /TMOFH P3 /TMOFL P3 /UD Figure 8.2 Port 3 Pin Configuration 8.3.2 Register Configuration and Description Table 8.5 shows the port 3 register configuration.
Page 245 Section 8 I/O Ports Port Data Register 3 (PDR3) Initial value Read/Write PDR3 is an 8-bit register that stores data for port 3 pins P3 to P3 . If port 3 is read while PCR3 bits are set to 1, the values stored in PDR3 are read, regardless of the actual pin states. If port 3 is read while PCR3 bits are cleared to 0, the pin states are read.
Page 246 Section 8 I/O Ports Port Pull-Up Control Register 3 (PUCR3) PUCR3 PUCR3 PUCR3 PUCR3 PUCR3 PUCR3 PUCR3 PUCR3 Initial value Read/Write PUCR3 controls whether the MOS pull-up of each of the port 3 pins P3 to P3 is on or off. When a PCR3 bit is cleared to 0, setting the corresponding PUCR3 bit to 1 turns on the MOS pull-up for the corresponding pin, while clearing the bit to 0 turns off the MOS pull-up.
Page 247 Section 8 I/O Ports Port Mode Register 3 (PMR3)    AEVL AEVH TMOFH TMOFL    Initial value Read/Write PMR3 is an 8-bit read/write register, controlling the selection of pin functions for port 3 pins. Bit 7—P3 /AEVL Pin Function Switch (AEVL) This bit selects whether pin P3 /AEVL is used as P3...
Page 248 Section 8 I/O Ports Bit 1—P3 /TMOFL Pin Function Switch (TMOFL) This bit selects whether pin P3 /TMOFL is used as P3 or as TMOFL. Bit 1 TMOFL Description Functions as P3 I/O pin (initial value) Functions as TMOFL output pin Bit 0—P3 /UD Pin Function Switch (UD) This bit selects whether pin P3...
Page 249: Pin Functions
Section 8 I/O Ports 8.3.3 Pin Functions Table 8.6 shows the port 3 pin functions. Table 8.6 Port 3 Pin Functions Pin Functions and Selection Method /AEVL The pin function depends on bit AEVL in PMR3 and bit PCR3 in PCR3. AEVL PCR3 Pin function...
Page 250: Pin States
Section 8 I/O Ports 8.3.4 Pin States Table 8.7 shows the port 3 pin states in each operating mode. Table 8.7 Port 3 Pin States Pins Reset Sleep Subsleep Standby Watch Subactive Active Functional Functional /AEVL High- Retains Retains High- Retains impedance * impedance...
Page 251: Port 4
Section 8 I/O Ports Port 4 8.4.1 Overview Port 4 is a 3-bit I/O port and 1-bit input port, configured as shown in figure 8.3. /IRQ /TXD Port 4 /RXD /SCK Figure 8.3 Port 4 Pin Configuration 8.4.2 Register Configuration and Description Table 8.8 shows the port 4 register configuration.
Page 252 Section 8 I/O Ports Port Control Register 4 (PCR4)      PCR4 PCR4 PCR4 Initial value      Read/Write PCR4 is an 8-bit register for controlling whether each of port 4 pins P4 to P4 functions as an input pin or output pin.
Page 253: Pin Functions
Section 8 I/O Ports 8.4.3 Pin Functions Table 8.9 shows the port 4 pin functions. Table 8.9 Port 4 Pin Functions Pin Functions and Selection Method The pin function depends on bit IRQ0 in PMR2. I R Q IRQ0 Pin function input pin input pin I R Q...
Page 254: Pin States
Section 8 I/O Ports 8.4.4 Pin States Table 8.10 shows the port 4 pin states in each operating mode. Table 8.10 Port 4 Pin States Pins Reset Sleep Subsleep Standby Watch Subactive Active High- Retains Retains High- Retains Functional Functional I R Q /TXD impedance...
Page 255: Port 5
Section 8 I/O Ports Port 5 8.5.1 Overview Port 5 is an 8-bit I/O port, configured as shown in figure 8.4. /WKP /SEG /WKP /SEG /WKP /SEG /WKP /SEG Port 5 /WKP /SEG /WKP /SEG /WKP /SEG /WKP /SEG Figure 8.4 Port 5 Pin Configuration 8.5.2 Register Configuration and Description Table 8.11 shows the port 5 register configuration.
Page 256 Section 8 I/O Ports Port Data Register 5 (PDR5) Initial value Read/Write PDR5 is an 8-bit register that stores data for port 5 pins P5 to P5 . If port 5 is read while PCR5 bits are set to 1, the values stored in PDR5 are read, regardless of the actual pin states. If port 5 is read while PCR5 bits are cleared to 0, the pin states are read.
Page 257 Section 8 I/O Ports Port Pull-Up Control Register 5 (PUCR5) PUCR5 PUCR5 PUCR5 PUCR5 PUCR5 PUCR5 PUCR5 PUCR5 Initial value Read/Write PUCR5 controls whether the MOS pull-up of each of port 5 pins P5 to P5 is on or off. When a PCR5 bit is cleared to 0, setting the corresponding PUCR5 bit to 1 turns on the MOS pull-up for the corresponding pin, while clearing the bit to 0 turns off the MOS pull-up.
Page 258: Pin Functions
Section 8 I/O Ports 8.5.3 Pin Functions Table 8.12 shows the port 5 pin functions. Table 8.12 Port 5 Pin Functions Pin Functions and Selection Method The pin function depends on bits WKP to WKP in PMR5, bits PCR5 to PCR5 W K P in PCR5, and bits SGS3 to SGS0 in LPCR.
Page 259: Pin States
Section 8 I/O Ports 8.5.4 Pin States Table 8.13 shows the port 5 pin states in each operating mode. Table 8.13 Port 5 Pin States Pins Reset Sleep Subsleep Standby Watch Subactive Active Functional Functional High- Retains Retains High- Retains W K P impedance * impedance...
Page 260: Port 6
Section 8 I/O Ports Port 6 8.6.1 Overview Port 6 is an 8-bit I/O port. The port 6 pin configuration is shown in figure 8.5. /SEG /SEG /SEG /SEG Port 6 /SEG /SEG /SEG /SEG Figure 8.5 Port 6 Pin Configuration 8.6.2 Register Configuration and Description Table 8.14 shows the port 6 register configuration.
Page 261 Section 8 I/O Ports Port Data Register 6 (PDR6) Initial value Read/Write PDR6 is an 8-bit register that stores data for port 6 pins P6 to P6 If port 6 is read while PCR6 bits are set to 1, the values stored in PDR6 are read, regardless of the actual pin states.
Page 262: Pin Functions
Section 8 I/O Ports Port Pull-Up Control Register 6 (PUCR6) PUCR6 PUCR6 PUCR6 PUCR6 PUCR6 PUCR6 PUCR6 PUCR6 Initial value Read/Write PUCR6 controls whether the MOS pull-up of each of the port 6 pins P6 to P6 is on or off. When a PCR6 bit is cleared to 0, setting the corresponding PUCR6 bit to 1 turns on the MOS pull-up for the corresponding pin, while clearing the bit to 0 turns off the MOS pull-up.
Page 263: Pin States
Section 8 I/O Ports 8.6.4 Pin States Table 8.16 shows the port 6 pin states in each operating mode. Table 8.16 Port 6 Pin States Reset Sleep Subsleep Standby Watch Subactive Active Functional Functional /SEG High- Retains Retains High- Retains impedance * /SEG impedance...
Page 264: Port 7
Section 8 I/O Ports Port 7 8.7.1 Overview Port 7 is an 8-bit I/O port, configured as shown in figure 8.6. /SEG /SEG /SEG /SEG Port 7 /SEG /SEG /SEG /SEG Figure 8.6 Port 7 Pin Configuration 8.7.2 Register Configuration and Description Table 8.17 shows the port 7 register configuration.
Page 265 Section 8 I/O Ports Port Data Register 7 (PDR7) Initial value Read/Write PDR7 is an 8-bit register that stores data for port 7 pins P7 to P7 . If port 7 is read while PCR7 bits are set to 1, the values stored in PDR7 are read, regardless of the actual pin states. If port 7 is read while PCR7 bits are cleared to 0, the pin states are read.
Page 266: Pin Functions
Section 8 I/O Ports 8.7.3 Pin Functions Table 8.18 shows the port 7 pin functions. Table 8.18 Port 7 Pin Functions Pin Functions and Selection Method /SEG The pin function depends on bits PCR7 to PCR7 in PCR7 and bits SGS3 to /SEG SGS0 in LPCR.
Page 267: Port 8
Section 8 I/O Ports Port 8 8.8.1 Overview Port 8 is an 8-bit I/O port configured as shown in figure 8.7. /SEG /SEG /SEG /SEG Port 8 /SEG /SEG /SEG /SEG Figure 8.7 Port 8 Pin Configuration 8.8.2 Register Configuration and Description Table 8.20 shows the port 8 register configuration.
Page 268 Section 8 I/O Ports Port Data Register 8 (PDR8) Initial value Read/Write PDR8 is an 8-bit register that stores data for port 8 pins P8 to P8 . If port 8 is read while PCR8 bits are set to 1, the values stored in PDR8 are read, regardless of the actual pin states. If port 8 is read while PCR8 bits are cleared to 0, the pin states are read.
Page 269: Pin Functions
Section 8 I/O Ports 8.8.3 Pin Functions Table 8.21 shows the port 8 pin functions. Table 8.21 Port 8 Pin Functions Pin Functions and Selection Method /SEG The pin function depends on bits PCR8 to PCR8 in PCR8 and bits SGS3 to SGS0 in LPCR.
Page 270: Port 9
Section 8 I/O Ports Port 9 8.9.1 Overview Port 9 is a 6-bit output port, configured as shown in figure 8.8. Port 9 /PWM /PWM Note: * The V pin is implemented on the H8/38124 Group only. Figure 8.8 Port 9 Pin Configuration Rev.
Page 271: Register Configuration And Description
Section 8 I/O Ports 8.9.2 Register Configuration and Description Table 8.23 shows the port 9 register configuration. Table 8.23 Port 9 Registers Name Abbr. Initial Value Address Port data register 9 PDR9 H'FF H'FFDC Port mode register 9 PMR9 — H'FFEC Port Data Register 9 (PDR9) —...
Page 272 Section 8 I/O Ports Bit 3— P9 to P9 Step-Up Circuit Control (PIOFF) Bit 3 turns the P9 to P9 step-up circuit on and off. This bit is reserved in the H8/38024S Group and H8/38124 Group. Bit 3 PIOFF Description Large-current port step-up circuit is turned on (initial value) Large-current port step-up circuit is turned off...
Page 273 Section 8 I/O Ports from 1 to 0 only when the PIOFF bit is cleared to 0. Also, if a large current flow is required, the PIOFF bit should be set to 1 and all the port data bits set to 1. Then clear PIOFF to 0 and, after allowing 30 clock cycles to permit stabilization of the voltage boost circuit, clear the port data bits to 0.
Page 274: Pin Functions
Section 8 I/O Ports 8.9.3 Pin Functions Table 8.24 shows the port 9 pin functions. Table 8.24 Port 9 Pin Functions Pin Functions and Selection Method VREFSEL Pin function output pin input pin /PWM (n = 1 or 0) /PWM PMR9 Pin function output pin...
Page 275: Port A
Section 8 I/O Ports 8.10 Port A 8.10.1 Overview Port A is a 4-bit I/O port, configured as shown in figure 8.9. /COM /COM Port A /COM /COM Figure 8.9 Port A Pin Configuration 8.10.2 Register Configuration and Description Table 8.26 shows the port A register configuration. Table 8.26 Port A Registers Name Abbr.
Page 276 Section 8 I/O Ports Port Control Register A (PCRA)     PCRA PCRA PCRA PCRA Initial value     Read/Write PCRA controls whether each of port A pins PA to PA functions as an input pin or output pin. Setting a PCRA bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin.
Page 277: Pin Functions
Section 8 I/O Ports 8.10.3 Pin Functions Table 8.27 shows the port A pin functions. Table 8.27 Port A Pin Functions Pin Functions and Selection Method /COM The pin function depends on bit PCRA in PCRA and bits SGS3 to SGS0. SGS3 to SGS0 0000 0000...
Page 278: Pin States
Section 8 I/O Ports 8.10.4 Pin States Table 8.28 shows the port A pin states in each operating mode. Table 8.28 Port A Pin States Pins Reset Sleep Subsleep Standby Watch Subactive Active Functional Functional /COM High- Retains Retains High- Retains impedance impedance...
Page 279: Port B
Section 8 I/O Ports 8.11 Port B 8.11.1 Overview Port B is an 8-bit input-only port, configured as shown in figure 8.10. Port B /IRQ /TMIC /extU * /extD * Note: * The extU and extD pins are implemented on the H8/38124 Group only. Figure 8.10 Port B Pin Configuration 8.11.2 Register Configuration and Description...
Page 280 Section 8 I/O Ports Port Data Register B (PDRB) Read/Write Reading PDRB always gives the pin states. However, if a port B pin is selected as an analog input channel for the A/D converter by AMR bits CH3 to CH0, that pin reads 0 regardless of the input voltage.
Page 281: Pin Functions
Section 8 I/O Ports 8.11.3 Pin Functions Table 8.30 shows the port B pin functions. Table 8.30 Port B Pin Functions Pin Functions and Selection Method The pin function depends on bits CH3 to CH0 in AMR. CH3 to CH0 Not 1011 1011 Pin function...
Page 282: Input/Output Data Inversion Function
Section 8 I/O Ports Pin Functions and Selection Method /extU Switching is accomplished by combining CH3 to CH0 in AMR and VINTUSEL in LVDCR as shown below. Note that VINTUSEL is implemented on the H8/38124 Group only. VINTUSEL CH3 to CH0 Not B'0101 B'0101 Pin function...
Page 283: Register Configuration And Descriptions
Section 8 I/O Ports 8.12.2 Register Configuration and Descriptions Table 8.31 shows the registers used by the input/output data inversion function. Table 8.31 Register Configuration Name Abbr. Address Serial port control register SPCR H'FF91 Serial Port Control Register (SPCR)  ...
Page 284: Note On Modification Of Serial Port Control Register
Section 8 I/O Ports Bit 3—TXD Pin Output Data Inversion Switch Bit 3 specifies whether or not TXD pin output data is to be inverted. Bit 3 SCINV3 Description output data is not inverted (initial value) output data is inverted Bit 2—RXD Pin Input Data Inversion Switch Bit 2 specifies whether or not RXD...
Page 285: Application Note
Section 8 I/O Ports 8.13 Application Note 8.13.1 The Management of the Un-Use Terminal If an I/O pin not used by the user system is floating, pull it up or down. • If an unused pin is an input pin, handle it in one of the following ways: ...
Page 286 Section 8 I/O Ports Rev. 7.00 Mar 10, 2005 page 244 of 652 REJ09B0042-0700...
Page 287: Section 9 Timers
Section 9 Timers Section 9 Timers Overview This LSI provides six timers: timers A, C, F, G, and a watchdog timer, and an asynchronous event counter. The functions of these timers are outlined in table 9.1. Table 9.1 Timer Functions Event Waveform Name...
Page 288: Timer A
Section 9 Timers Event Waveform Name Functions Internal Clock Input Pin Output Pin Remarks φ/2 to φ/8 • Asynchro- 16-bit counter AEVL — nous event (3 choices) AEVH • Also usable as two counter IRQAEC independent 8-bit counters • Counts events asynchronous to φ...
Page 289 Section 9 Timers Block Diagram Figure 9.1 shows a block diagram of timer A. φ φ φ /128 φ/8192, φ/4096, φ/2048, φ/512, φ/256, φ/128, φ/32, φ/8 φ IRRTA [Legend] TMA: Timer mode register A TCA: Timer counter A IRRTA: Timer A overflow interrupt request flag PSW: Prescaler W PSS:...
Page 290: Register Descriptions
Section 9 Timers Register Configuration Table 9.2 shows the register configuration of timer A. Table 9.2 Timer A Registers Name Abbr. Initial Value Address Timer mode register A — H'FFB0 Timer counter A H'00 H'FFB1 Clock stop register 1 CKSTPR1 H'FF H'FFFA 9.2.2...
Page 291 Section 9 Timers Bits 3 to 0—Internal Clock Select (TMA3 to TMA0) Bits 3 to 0 select the clock input to TCA. The selection is made as follows. Description Bit 3 Bit 2 Bit 1 Bit 0 Prescaler and Divider Ratio TMA3 TMA2 TMA1...
Page 292 Section 9 Timers Timer Counter A (TCA) TCA7 TCA6 TCA5 TCA4 TCA3 TCA2 TCA1 TCA0 Initial value Read/Write TCA is an 8-bit read-only up-counter, which is incremented by internal clock input. The clock source for input to this counter is selected by bits TMA3 to TMA0 in timer mode register A (TMA).
Page 293: Timer Operation
Section 9 Timers 9.2.3 Timer Operation Interval Timer Operation When bit TMA3 in timer mode register A (TMA) is cleared to 0, timer A functions as an 8-bit interval timer. Upon reset, TCA is cleared to H'00 and bit TMA3 is cleared to 0, so up-counting and interval timing resume immediately.
Page 294: Timer A Operation States
Section 9 Timers 9.2.4 Timer A Operation States Table 9.3 summarizes the timer A operation states. Table 9.3 Timer A Operation States Sub- Sub- Module Operation Mode Reset Active Sleep Watch active sleep Standby Standby TCA Interval Reset Functions Functions Halted Halted Halted Halted...
Page 295: Timer C
Section 9 Timers Timer C 9.3.1 Overview Timer C is an 8-bit timer that increments or decrements each time a clock pulse is input. This timer has two operation modes, interval and auto reload. Features Features of timer C are given below. •...
Page 296 Section 9 Timers Block Diagram Figure 9.2 shows a block diagram of timer C. φ TMIC φ IRRTC [Legend] TMC: Timer mode register C TCC: Timer counter C TLC: Timer load register C IRRTC: Timer C overflow interrupt request flag PSS: Prescaler S Figure 9.2 Block Diagram of Timer C...
Page 297: Register Descriptions
Section 9 Timers Register Configuration Table 9.5 shows the register configuration of timer C. Table 9.5 Timer C Registers Name Abbr. Initial Value Address Timer mode register C H'18 H'FFB4 Timer counter C H'00 H'FFB5 Timer load register C H'00 H'FFB5 Clock stop register 1 CKSTPR1...
Page 298 Section 9 Timers Bits 6 and 5—Counter Up/Down Control (TMC6, TMC5) Selects whether TCC up/down control is performed by hardware using UD pin input, or whether TCC functions as an up-counter or a down-counter. Bit 6 Bit 5 TMC6 TMC5 Description TCC is an up-counter (initial value)
Page 299 Section 9 Timers Timer Counter C (TCC) TCC7 TCC6 TCC5 TCC4 TCC3 TCC2 TCC1 TCC0 Initial value Read/Write TCC is an 8-bit read-only up/down-counter, which is incremented or decremented by internal clock or external event input. The clock source for input to this counter is selected by bits TMC2 to TMC0 in timer mode register C (TMC).
Page 300: Timer Operation
Section 9 Timers Clock Stop Register 1 (CKSTPR1) Bit:   S32CKSTP ADCKSTP TGCKSTP TFCKSTP TCCKSTP TACKSTP Initial value:   Read/Write: CKSTPR1 is an 8-bit read/write register that performs module standby mode control for peripheral modules. Only the bit relating to timer C is described here. For details of the other bits, see the sections on the relevant modules.
Page 301 Section 9 Timers During interval timer operation (TMC7 = 0), when a value is set in timer load register C (TLC), the same value is set in TCC. Note: For details on interrupts, see section 3.3, Interrupts. Auto-Reload Timer Operation Setting bit TMC7 in TMC to 1 causes timer C to function as an 8-bit auto-reload timer.
Page 302: Timer C Operation States
Section 9 Timers 9.3.4 Timer C Operation States Table 9.6 summarizes the timer C operation states. Table 9.6 Timer C Operation States Sub- Sub- Module Operation Mode Reset Active Sleep Watch active sleep Standby Standby Interval Reset Functions Functions Halted Functions/ Functions/ Halted...
Page 303: Timer F
Section 9 Timers Timer F 9.4.1 Overview Timer F is a 16-bit timer with a built-in output compare function. As well as counting external events, timer F also provides for counter resetting, interrupt request generation, toggle output, etc., using compare match signals. Timer F can also be used as two independent 8-bit timers (timer FH and timer FL).
Page 304 Section 9 Timers Block Diagram Figure 9.3 shows a block diagram of timer F. φ IRRTFL TCRF φ TCFL TMIF Toggle Comparator TMOFL circuit OCRFL TCFH Toggle Match TMOFH Comparator circuit OCRFH TCSRF IRRTFH [Legend] TCRF: Timer control register F TCSRF: Timer control/status register F TCFH:...
Page 305 Section 9 Timers Pin Configuration Table 9.7 shows the timer F pin configuration. Table 9.7 Pin Configuration Name Abbr. Function Timer F event input TMIF Input Event input pin for input to TCFL Timer FH output TMOFH Output Timer FH toggle output pin Timer FL output TMOFL Output...
Page 306: Register Descriptions
Section 9 Timers 9.4.2 Register Descriptions 16-bit Timer Counter (TCF) 8-bit Timer Counter (TCFH) 8-bit Timer Counter (TCFL) Bit: Initial value: Read/Write: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCFH TCFL TCF is a 16-bit read/write up-counter configured by cascaded connection of 8-bit timer counters TCFH and TCFL.
Page 307 Section 9 Timers 16-bit Output Compare Register (OCRF) 8-bit Output Compare Register (OCRFH) 8-bit Output Compare Register (OCRFL) OCRF Bit: Initial value: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Read/Write: OCRFH OCRFL OCRF is a 16-bit read/write register composed of the two registers OCRFH and OCRFL.
Page 308 Section 9 Timers Timer Control Register F (TCRF) Bit: TOLH CKSH2 CKSH1 CKSH0 TOLL CKSL2 CKSL1 CKSL0 Initial value: Read/Write: TCRF is an 8-bit write-only register that switches between 16-bit mode and 8-bit mode, selects the input clock from among four internal clock sources or external event input, and sets the output level of the TMOFH and TMOFL pins.
Page 309 Section 9 Timers Bit 3—Toggle Output Level L (TOLL) Bit 3 sets the TMOFL pin output level. The output level is effective immediately after this bit is written. Bit 3 TOLL Description Low level (initial value) High level Bits 2 to 0—Clock Select L (CKSL2 to CKSL0) Bits 2 to 0 select the clock input to TCFL from among four internal clock sources or external event input.
Page 310 Section 9 Timers Timer Control/Status Register F (TCSRF) Bit: OVFH CMFH OVIEH CCLRH OVFL CMFL OVIEL CCLRL Initial value: R/(W) * R/(W) * R/(W) * R/(W) * Read/Write: Note: * Bits 7, 6, 3, and 2 can only be written with 0, for flag clearing. TCSRF is an 8-bit read/write register that performs counter clear selection, overflow flag setting, and compare match flag setting, and controls enabling of overflow interrupt requests.
Page 311 Section 9 Timers Bit 5—Timer Overflow Interrupt Enable H (OVIEH) Bit 5 selects enabling or disabling of interrupt generation when TCFH overflows. Bit 5 OVIEH Description TCFH overflow interrupt request is disabled (initial value) TCFH overflow interrupt request is enabled Bit 4—Counter Clear H (CCLRH) In 16-bit mode, bit 4 selects whether TCF is cleared when TCF and OCRF match.
Page 312 Section 9 Timers Bit 2—Compare Match Flag L (CMFL) Bit 2 is a status flag indicating that TCFL has matched OCRFL. This flag is set by hardware and cleared by software. It cannot be set by software. Bit 2 CMFL Description Clearing condition: (initial value)
Page 313: Cpu Interface
Section 9 Timers Clock Stop Register 1 (CKSTPR1) Bit:   S32CKSTP ADCKSTP TGCKSTP TFCKSTP TCCKSTP TACKSTP Initial value:   Read/Write: CKSTPR1 is an 8-bit read/write register that performs module standby mode control for peripheral modules. Only the bit relating to timer F is described here. For details of the other bits, see the sections on the relevant modules.
Page 314 Section 9 Timers Figure 9.4 shows an example in which H'AA55 is written to TCF. Write to upper byte Module data bus interface (H'AA) TEMP (H'AA) TCFH TCFL Write to lower byte Module data bus interface (H'55) TEMP (H'AA) TCFH TCFL (H'AA) (H'55)
Page 315 Section 9 Timers Read Access In access to TCF, when the upper byte is read the upper-byte data is transferred directly to the CPU and the lower-byte data is transferred to TEMP. Next, when the lower byte is read, the lower-byte data in TEMP is transferred to the CPU.
Page 316: Operation
Section 9 Timers 9.4.4 Operation Timer F is a 16-bit counter that increments on each input clock pulse. The timer F value is constantly compared with the value set in output compare register F, and the counter can be cleared, an interrupt requested, or port output toggled, when the two values match. Timer F can also function as two independent 8-bit timers.
Page 317 Section 9 Timers TCF Increment Timing TCF is incremented by clock input (internal clock or external event input). a. Internal clock operation Bits CKSH2 to CKSH0 or CKSL2 to CKSL0 in TCRF select one of four internal clock sources (φ/32, φ/16, φ/4, or φw/4) created by dividing the system clock (φ or φw). b.
Page 318 Section 9 Timers TCF Clear Timing TCF can be cleared by a compare match with OCRF. Timer Overflow Flag (OVF) Set Timing OVF is set to 1 when TCF overflows from H'FFFF to H'0000. Compare Match Flag Set Timing The compare match flag (CMFH or CMFL) is set to 1 when the TCF and OCRF values match. The compare match signal is generated in the last state during which the values match (when TCF is updated from the matching value to a new value).
Page 319: Application Notes
Section 9 Timers 9.4.5 Application Notes The following types of contention and operation can occur when timer F is used. 16-bit Timer Mode In toggle output, TMOFH pin output is toggled when all 16 bits match and a compare match signal is generated.
Page 320 Section 9 Timers b. TCFL, OCRFL In toggle output, TMOFL pin output is toggled when a compare match occurs. If a TCRF write by a MOV instruction and generation of the compare match signal occur simultaneously, TOLL data is output to the TMOFL pin as a result of the TCRF write. If an OCRFL write and compare match signal generation occur simultaneously, the compare match signal is invalid.
Page 321 Section 9 Timers The term of validity of “Interrupt factor generation signal” = 1 cycle of φw + waiting time for completion of executing instruction + interrupt time synchronized with φ = 1/φw + ST • (1/φ) + (2/φ) (second)..(1) ST: Executing number of execution states Method 1 is recommended to operate for time efficiency.
Page 322 Section 9 Timers Interrupt request Interrupt request flag clear flag clear Program process Interrupt Interrupt Normal φ Interrupt factor generation signal (Internal signal, nega-active) Overflow signal, Compare match signal (Internal signal, nega-active) Interrupt request flag (IRRTFH, IRRTFL) Figure 9.7 Clear Interrupt Request Flag when Interrupt Factor Generation Signal is Valid Timer Counter (TCF) Read/Write When φw/4 is selected as the internal clock in active (high-speed, medium-speed) mode, write on TCF is impossible.
Page 323: Timer G
Section 9 Timers Timer G 9.5.1 Overview Timer G is an 8-bit timer with dedicated input capture functions for the rising/falling edges of pulses input from the input capture input pin (input capture input signal). High-frequency component noise in the input capture input signal can be eliminated by a noise canceler, enabling accurate measurement of the input capture input signal duty cycle.
Page 324 Section 9 Timers Block Diagram Figure 9.8 shows a block diagram of timer G. φ Level detector φ ICRGF Noise Edge TMIG canceler detector ICRGR IRRTG [Legend] TMG: Timer mode register G TCG: Timer counter G ICRGF: Input capture register GF ICRGR: Input capture register GR IRRTG:...
Page 325: Register Descriptions
Section 9 Timers Register Configuration Table 9.11 shows the register configuration of timer G. Table 9.11 Timer G Registers Name Abbr. Initial Value Address Timer control register G H'00 H'FFBC Timer counter G — H'00 — Input capture register GF ICRGF H'00 H'FFBD...
Page 326 Section 9 Timers Input Capture Register GF (ICRGF) Bit: ICRGF7 ICRGF6 ICRGF5 ICRGF4 ICRGF3 ICRGF2 ICRGF1 ICRGF0 Initial value: Read/Write: ICRGF is an 8-bit read-only register. When a falling edge of the input capture input signal is detected, the current TCG value is transferred to ICRGF. If IIEGS in TMG is 1 at this time, IRRTG in IRR2 is set to 1, and if IENTG in IENR2 is 1, an interrupt request is sent to the CPU.
Page 327 Section 9 Timers Timer Mode Register G (TMG) Bit: OVFH OVFL OVIE IIEGS CCLR1 CCLR0 CKS1 CKS0 Initial value: R/(W) * R/(W) * Read/Write: Note: * Bits 7 and 6 can only be written with 0, for flag clearing. TMG is an 8-bit read/write register that performs TCG clock selection from four internal clock sources, counter clear selection, and edge selection for the input capture input signal interrupt request, controls enabling of overflow interrupt requests, and also contains the overflow flags.
Page 328 Section 9 Timers Bit 5—Timer Overflow Interrupt Enable (OVIE) Bit 5 selects enabling or disabling of interrupt generation when TCG overflows. Bit 5 OVIE Description TCG overflow interrupt request is disabled (initial value) TCG overflow interrupt request is enabled Bit 4—Input Capture Interrupt Edge Select (IIEGS) Bit 4 selects the input capture input signal edge that generates an interrupt request.
Page 329 Section 9 Timers Bits 1 and 0—Clock Select (CKS1, CKS0) Bits 1 and 0 select the clock input to TCG from among four internal clock sources. Bit 1 Bit 0 CKS1 CKS0 Description Internal clock: counting on φ/64 (initial value) Internal clock: counting on φ/32 Internal clock: counting on φ/2 Internal clock: counting on φw/4...
Page 330: Noise Canceler
Section 9 Timers 9.5.3 Noise Canceler The noise canceler consists of a digital low-pass filter that eliminates high-frequency component noise from the pulses input from the input capture input pin. The noise canceler is set by NCS * in PMR2. Figure 9.9 shows a block diagram of the noise canceler.
Page 331 Section 9 Timers In this example, high-level input of less than five times the width of the sampling clock at the input capture input pin is eliminated as noise. Input capture input signal Sampling clock Noise canceler output Eliminated as noise Figure 9.10 Noise Canceler Timing (Example) Rev.
Page 332: Operation
Section 9 Timers 9.5.4 Operation Timer G is an 8-bit timer with built-in input capture and interval functions. Timer G Functions Timer G is an 8-bit up-counter with two functions, an input capture timer function and an interval timer function. The operation of these two functions is described below.
Page 333 Section 9 Timers b. Interval timer operation When the TMIG bit in PMR1 is cleared to 0, timer G functions as an interval timer. Following a reset, TCG starts counting on the φ/64 internal clock. The input clock can be selected from four internal clock sources by bits CKS1 and CKS0 in TMG.
Page 334 Section 9 Timers b. With noise cancellation function When noise cancellation is performed on the input capture input, the passage of the input capture signal through the noise canceler results in a delay of five sampling clock cycles from the input capture input signal edge. Figure 9.12 shows the timing in this case.
Page 335 Section 9 Timers TCG Clear Timing TCG can be cleared by the rising edge, falling edge, or both edges of the input capture input signal. Figure 9.14 shows the timing for clearing by both edges. Input capture input signal Input capture signal F Input capture signal R...
Page 336 Section 9 Timers Timer G Operation Modes Timer G operation modes are shown in table 9.12. Table 9.12 Timer G Operation Modes Module Operation Mode Reset Active Sleep Watch Subactive Subsleep Standby Standby Reset Functions * Functions * Functions/ Input capture Functions/ Functions/ Halted...
Page 337: Application Notes
Section 9 Timers 9.5.5 Application Notes Internal Clock Switching and TCG Operation Depending on the timing, TCG may be incremented by a switch between different internal clock sources. Table 9.13 shows the relation between internal clock switchover timing (by write to bits CKS1 and CKS0) and TCG operation.
Page 338 Section 9 Timers Clock Levels Before and After Modifying Bits CKS1 and CKS0 TCG Operation Goes from high level to low level Clock before switching Clock after switching Count clock Write to CKS1 and CKS0 Goes from high level to high level Clock before switching Clock after...
Page 339 Section 9 Timers Table 9.14 Input Capture Input Signal Input Edges Due to Input Capture Input Pin Switching, and Conditions for Their Occurrence Input Capture Input Signal Input Edge Conditions Generation of rising edge When TMIG is modified from 0 to 1 while the TMIG pin is high When NCS is modified from 0 to 1 while the TMIG pin is high, then TMIG is modified from 0 to 1 before the signal is sampled five times by the noise canceler...
Page 340 Section 9 Timers When the pin function is switched and an edge is generated in the input capture input signal, if this edge matches the edge selected by the input capture interrupt select (IIEGS) bit, the interrupt request flag will be set to 1. The interrupt request flag should therefore be cleared to 0 before use. Figure 9.15 shows the procedure for port mode register manipulation and interrupt request flag clearing.
Page 341: Timer G Application Example
Section 9 Timers 9.5.6 Timer G Application Example Using timer G, it is possible to measure the high and low widths of the input capture input signal as absolute values. For this purpose, CCLR1 and CCLR0 in TMG should both be set to 1. Figure 9.16 shows an example of the operation in this case.
Page 342: Watchdog Timer
Section 9 Timers Watchdog Timer 9.6.1 Overview The watchdog timer has an 8-bit counter that is incremented by an input clock. If a system runaway allows the counter value to overflow before being rewritten, the watchdog timer can reset the chip internally. Note that stabilization times for the H8/38024, H8/38024S, and H8/38024R Group and for the H8/38124 Group are different.
Page 343 Section 9 Timers Block Diagram Figures 9.17(1) and 9.17(2) show a block diagram of the watchdog timer. TCSRW φ φ/8192 φ [Legend] Reset TCSRW: Timer control/status register W signal TCW: Timer counter W PSS: Prescaler S Figure 9.17(1) Block Diagram of Watchdog Timer (H8/38024, H8/38024S, H8/38024R Group) Rev.
Page 344 Section 9 Timers Watchdog on-chip TCSRW oscillator φ φ Interrupt/reset Internal reset signal or controller interrupt request signal [Legend] TCSRW: Timer control/status register W TCW: Timer counter W TMW: Timer mode register W PSS: Prescaler S Figure 9.17(2) Block Diagram of Watchdog Timer (H8/38124 Group) Register Configuration Table 9.16 shows the register configuration of the watchdog timer.
Page 345: Register Descriptions
Section 9 Timers 9.6.2 Register Descriptions Timer Control/Status Register W (TCSRW) B6WI TCWE B4WI TCSRWE B2WI WDON B0WI WRST Initial value Read/Write (R/W) (R/W) (R/W) (R/W) Notes: 1. Write is enabled only under certain conditions, which are given in the descriptions of the individual bits.
Page 346 Section 9 Timers Bit 5—Bit 4 Write Disable (B4WI) Bit 5 controls the writing of data to bit 4 in TCSRW. Bit 5 B4WI Description Bit 4 is write-enabled Bit 4 is write-protected (initial value) This bit is always read as 1. Data written to this bit is not stored. Bit 4—Timer Control/Status Register W Write Enable (TCSRWE) Bit 4 controls the writing of data to bits 2 and 0 in TCSRW.
Page 347 Section 9 Timers Bit 2 WDON Description (initial value) * Watchdog timer operation is disabled Clearing conditions: Reset, or when TCSRWE is set to 1 and 0 is written to B2WI and WDON. Note that a reset clears WDON to 0 on the H8/38024, H8/38024S, and H8/38024R Group, but sets WDON to 1 on the H8/38124 Group.
Page 348 Section 9 Timers Timer Counter W (TCW) TCW7 TCW6 TCW5 TCW4 TCW3 TCW2 TCW1 TCW0 Initial value Read/Write For the H8/38024, H8/38024S, and H8/38024R groups, the clock source is φ/8,192 or φw/32. For the H8/38124 group, the clock source is selected based on the timer mode register (TMW) setting if WDCKS is 0 and is φw/32 if WDCKS is 1.
Page 349 Section 9 Timers Bit 3 Bit 2 Bit 1 Bit 0 CKS3 CKS2 CKS1 CKS0 Description Internal clock: φ/64 count Internal clock: φ/128 count Internal clock: φ/256 count Internal clock: φ/512 count Internal clock: φ/1024 count Internal clock: φ/2048 count Internal clock: φ/4096 count Internal clock: φ/8192 count (initial value)
Page 350 Section 9 Timers Port Mode Register 2 (PMR2) — — POF1 — — WDCKS IRQ0 Initial value Read/Write — — — — PMR2 is an 8-bit read/write register, mainly controlling the selection of pin functions for port 2. Only the bit relating to the watchdog timer is described here. For details of the other bits, see section 8, I/O Ports.
Page 351: Timer Operation
Section 9 Timers 9.6.3 Timer Operation The watchdog timer has an 8-bit counter (TCW) that is incremented by clock input. The input clock is selected by the WDCKS in port mode register 2 (PMR2): on the H8/38024, H8/38024S, and H8/38024R Group, φ/8192 is selected when WDCKS is cleared to 0, and φw/32 when set to 1. On the H8/38124 Group, if WDCKS is cleared to 0 the clock selection is specified by the setting of timer mode register W (TMW), and if WDCKS is set to 1 the φw/32 clock source is selected.
Page 352: Watchdog Timer Operation States
Section 9 Timers 9.6.4 Watchdog Timer Operation States Table 9.17(1) and table 9.17(2) summarize the watchdog timer operation states for the H8/38024, H8/38024S, and H8/38024R Group, and for the H8/38124 Group, respectively. Table 9.17(1) Watchdog Timer Operation States (H8/38024, H8/38024S, H8/38024R Group) Operation Module Mode...
Page 353: Asynchronous Event Counter (Aec)
Section 9 Timers Asynchronous Event Counter (AEC) 9.7.1 Overview The asynchronous event counter is incremented by external event clock or internal clock input. Features Features of the asynchronous event counter are given below. • Can count asynchronous events Can count external events input asynchronously without regard to the operation of base clocks φ...
Page 354 Section 9 Timers Block Diagram Figure 9.19 shows a block diagram of the asynchronous event counter. IRREC ECCR φ ECCSR φ/2 φ/4, φ/8 (8 bits) Edge sensing AEVH circuit (8 bits) Edge sensing AEVL circuit IRQAEC Edge sensing To CPU interrupt circuit (IRREC2) ECPWCRL...
Page 355 Section 9 Timers Pin Configuration Table 9.18 shows the asynchronous event counter pin configuration. Table 9.18 Pin Configuration Name Abbr. Function Asynchronous event input H AEVH Input Event input pin for input to event counter H Asynchronous event input L AEVL Input Event input pin for input to event counter L...
Page 356: Register Configurations
Section 9 Timers 9.7.2 Register Configurations Event Counter PWM Compare Register H (ECPWCRH) ECPWCRH7 ECPWCRH6 ECPWCRH5 ECPWCRH4 ECPWCRH3 ECPWCRH2 ECPWCRH1 ECPWCRH0 Initial value Read/Write Note: When ECPWME in AEGSR is 1, event counter PWM is operating and therefore ECPWCRH should not be modified. When changing the conversion period, event counter PWM must be halted by clearing ECPWME to 0 in AEGSR before modifying ECPWCRH.
Page 357 Section 9 Timers Event Counter PWM Data Register H (ECPWDRH) ECPWDRH7 ECPWDRH6 ECPWDRH5 ECPWDRH4 ECPWDRH3 ECPWDRH2 ECPWDRH1 ECPWDRH0 Initial value Read/Write Note: When ECPWME in AEGSR is 1, event counter PWM is operating and therefore ECPWDRH should not be modified. When changing the data, event counter PWM must be halted by clearing ECPWME to 0 in AEGSR before modifying ECPWDRH.
Page 358 Section 9 Timers Bits 7 and 6—AEC Edge Select H Bits 7 and 6 select rising, falling, or both edge sensing for the AEVH pin. Bit 7 Bit 6 AHEGS1 AHEGS0 Description Falling edge on AEVH pin is sensed (initial value) Rising edge on AEVH pin is sensed Both edges on AEVH pin are sensed Use prohibited...
Page 359 Section 9 Timers Bit 1—Event Counter PWM Enable Bit 1 controls enabling/disabling of event counter PWM and selection/deselection of IRQAEC. Bit 1 ECPWME Description AEC PWM halted, IRQAEC selected (initial value) AEC PWM operation enabled, IRQAEC deselected Bit 0—Reserved Bit 0 is a readable/writable reserved bit. It is initialized to 0 by a reset. Note: Do not set this bit to 1.
Page 360 Section 9 Timers Bits 5 and 4—AEC Clock Select L (ACKL1, ACKL0) Bits 5 and 4 select the clock used by ECL. Bit 5 Bit 4 ACKL1 ACKL0 Description AEVL pin input (initial value) φ/2 φ/4 φ/8 Bits 3 to 1—Event Counter PWM Clock Select (PWCK2, PWCK1, PWCK0) Bits 3 to 1 select the event counter PWM clock.
Page 361 Section 9 Timers Event Counter Control/Status Register (ECCSR)  CUEH CUEL CRCH CRCL Initial Value R/W * R/W * Read/Write Note: Bits 7 and 6 can only be written with 0, for flag clearing. ECCSR is an 8-bit read/write register that controls counter overflow detection, counter resetting, and halting of the count-up function.
Page 362 Section 9 Timers Bit 6 Description ECL has not overflowed (initial value) Clearing condition: After reading OVL = 1, cleared by writing 0 to OVL ECL has overflowed Setting condition: Set when ECL overflows from H'FF to H'00 Bit 5—Reserved Bit 5 is a readable/writable reserved bit.
Page 363 Section 9 Timers Bit 2—Count-up Enable L (CUEL) Bit 2 enables event clock input to ECL. When 1 is written to this bit, event clock input is enabled and increments the counter. When 0 is written to this bit, event clock input is disabled and the ECL value is held.
Page 364 Section 9 Timers ECH is an 8-bit read-only up-counter that operates either as an independent 8-bit event counter or as the upper 8-bit up-counter of a 16-bit event counter configured in combination with ECL. The external asynchronous event AEVH pin, φ/2, φ/4, φ/8, or the overflow signal from lower 8-bit counter ECL can be selected as the input clock source.
Page 365: Operation
Section 9 Timers 9.7.3 Operation 16-bit Event Counter Operation When bit CH2 is cleared to 0 in ECCSR, ECH and ECL operate as a 16-bit event counter. Any of four input clock sources—φ/2, φ/4, φ/8, or AEVL pin input—can be selected by means of bits ACKL1 and ACKL0 in ECCR.
Page 366 Section 9 Timers 8-bit Event Counter Operation When bit CH2 is set to 1 in ECCSR, ECH and ECL operate as independent 8-bit event counters. φ/2, φ/4, φ/8, or AEVH pin input can be selected as the input clock source for ECH by means of bits ACKH1 and ACKH0 in ECCR, and φ/2, φ/4, φ/8, or AEVL pin input can be selected as the input clock source for ECL by means of bits ACKL1 and ACKL0 in ECCR.
Page 367 Section 9 Timers IRQAEC Operation When ECPWME in AEGSR is 0, the ECH and ECL input clocks are enabled only when IRQAEC is high. When IRQAEC is low, the input clocks are not input to the counters, and so ECH and ECL do not count.
Page 368 Section 9 Timers Figure 9.22 and table 9.20 show examples of event counter PWM operation. = T × (N Clock input enabled time Clock input disabled time : One conversion period ECPWM input clock cycle Value of ECPWDRH and ECPWDRL Fixed low when Ndr = H'FFFF = T ×...
Page 369 Section 9 Timers Clock Input Enable/Disable Function Operation The clock input to the event counter can be controlled by the IRQAEC pin when ECPWME in AEGSR is 0, and by event counter PWM output IECPWM when ECPWME in AEGSR is 1. As this function forcibly terminates the clock input by each signal, a maximum error of one count will occur depending the IRQAEC or IECPWM timing.
Page 370: Asynchronous Event Counter Operation Modes
Section 9 Timers 9.7.4 Asynchronous Event Counter Operation Modes Asynchronous event counter operation modes are shown in table 9.21. Table 9.21 Asynchronous Event Counter Operation Modes Operation Module Mode Reset Active Sleep Watch Subactive Subsleep Standby Standby Functions Functions Retained * Retained * AEGSR Reset...
Page 371 Section 9 Timers Maximum AEVH/AEVL Pin Input Mode Clock Frequency Active (high-speed), sleep (high-speed) 16 MHz Active (medium-speed), sleep (medium-speed) (φ/16) 2 • f (φ/32) (φ/64) 1/2 • f = 1 MHz to 4 MHz (φ/128) 1/4 • f Watch, subactive, subsleep, standby (φw/2) 1000 kHz (φw/4)
Page 372 Section 9 Timers Rev. 7.00 Mar 10, 2005 page 330 of 652 REJ09B0042-0700...
Page 373: Section 10 Serial Communication Interface
Section 10 Serial Communication Interface Section 10 Serial Communication Interface 10.1 Overview The H8/38024 Group is provided with one serial communication interface, SCI3. Serial communication interface 3 (SCI3) can carry out serial data communication in either asynchronous or synchronous mode. It is also provided with a multiprocessor communication function that enables serial data to be transferred among processors.
Page 374 Section 10 Serial Communication Interface • Full-duplex communication Separate transmission and reception units are provided, enabling transmission and reception to be carried out simultaneously. The transmission and reception units are both double-buffered, allowing continuous transmission and reception. • On-chip baud rate generator, allowing any desired bit rate to be selected •...
Page 375: Block Diagram
Section 10 Serial Communication Interface 10.1.2 Block Diagram Figure 10.1 shows a block diagram of SCI3. Internal clock (φ/64, φ/16, φ /2, φ) External Baud rate generator clock Clock Transmit/receive SCR3 control circuit SPCR Interrupt request (TEI, TXI, RXI, ERI) [Legend] RSR: Receive shift register...
Page 376: Pin Configuration
Section 10 Serial Communication Interface 10.1.3 Pin Configuration Table 10.1 shows the SCI3 pin configuration. Table 10.1 Pin Configuration Name Abbr. Function SCI3 clock SCI3 clock input/output SCI3 receive data input Input SCI3 receive data input SCI3 transmit data output Output SCI3 transmit data output 10.1.4...
Page 377: Register Descriptions
Section 10 Serial Communication Interface 10.2 Register Descriptions 10.2.1 Receive Shift Register (RSR)         Read/Write RSR is a register used to receive serial data. Serial data input to RSR from the RXD pin is set in the order in which it is received, starting from the LSB (bit 0), and converted to parallel data.
Page 378: Transmit Shift Register (Tsr)
Section 10 Serial Communication Interface 10.2.3 Transmit Shift Register (TSR)         Read/Write TSR is a register used to transmit serial data. Transmit data is first transferred from TDR to TSR, and serial data transmission is carried out by sending the data to the TXD pin in order, starting from the LSB (bit 0).
Page 379: Serial Mode Register (Smr)
Section 10 Serial Communication Interface 10.2.5 Serial Mode Register (SMR) STOP CKS1 CKS0 Initial value Read/Write SMR is an 8-bit register used to set the serial data transfer format and to select the clock source for the baud rate generator. SMR can be read or written by the CPU at any time.
Page 380 Section 10 Serial Communication Interface Bit 5—Parity Enable (PE) Bit 5 selects whether a parity bit is to be added during transmission and checked during reception in asynchronous mode. In synchronous mode parity bit addition and checking is not performed, irrespective of the bit 5 setting.
Page 381 Section 10 Serial Communication Interface Bit 3—Stop Bit Length (STOP) Bit 3 selects 1 bit or 2 bits as the stop bit length in asynchronous mode. The STOP bit setting is only valid in asynchronous mode. When synchronous mode is selected the STOP bit setting is invalid since stop bits are not added.
Page 382: Serial Control Register 3 (Scr3)
Section 10 Serial Communication Interface Bits 1 and 0—Clock Select 1, 0 (CKS1, CKS0) Bits 1 and 0 choose φ/64, φ/16, φw/2, or φ as the clock source for the baud rate generator. For the relation between the clock source, bit rate register setting, and baud rate, see section 10.2.8, Bit rate register (BRR).
Page 383 Section 10 Serial Communication Interface Bit 7 Description Transmit data empty interrupt request (TXI) disabled (initial value) Transmit data empty interrupt request (TXI) enabled Bit 6—Receive Interrupt Enable (RIE) Bit 6 selects enabling or disabling of the receive data full interrupt request (RXI) and the receive error interrupt request (ERI) when receive data is transferred from the receive shift register (RSR) to the receive data register (RDR), and bit RDRF in the serial status register (SSR) is set to 1.
Page 384 Section 10 Serial Communication Interface Bit 4—Receive Enable (RE) Bit 4 selects enabling or disabling of the start of receive operation. Bit 4 Description Receive operation disabled * (RXD32 pin is I/O port) (initial value) Receive operation enabled * (RXD32 pin is receive data pin) Notes: 1.
Page 385 Section 10 Serial Communication Interface Bit 2—Transmit End Interrupt Enable (TEIE) Bit 2 selects enabling or disabling of the transmit end interrupt request (TEI) if there is no valid transmit data in TDR when MSB data is to be sent. Bit 2 TEIE Description...
Page 386: Serial Status Register (Ssr)
Section 10 Serial Communication Interface 10.2.7 Serial Status Register (SSR) TDRE RDRF TEND MPBR MPBT Initial value R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * Read/Write Note: * Only a write of 0 for flag clearing is possible. SSR is an 8-bit register containing status flags that indicate the operational status of SCI3, and multiprocessor bits.
Page 387 Section 10 Serial Communication Interface Bit 6—Receive Data Register Full (RDRF) Bit 6 indicates that received data is stored in RDR. Bit 6 RDRF Description There is no receive data in RDR (initial value) Clearing conditions: After reading RDRF = 1, cleared by writing 0 to RDRF When RDR data is read by an instruction There is receive data in RDR Setting condition:...
Page 388 Section 10 Serial Communication Interface Bit 4—Framing Error (FER) Bit 4 indicates that a framing error has occurred during reception in asynchronous mode. Bit 4 Description Reception in progress or completed * (initial value) Clearing condition: After reading FER = 1, cleared by writing 0 to FER A framing error has occurred during reception Setting condition: When the stop bit at the end of the receive data is checked for a value...
Page 389 Section 10 Serial Communication Interface Bit 2—Transmit End (TEND) Bit 2 indicates that bit TDRE is set to 1 when the last bit of a transmit character is sent. Bit 2 is a read-only bit and cannot be modified. Bit 2 TEND Description Transmission in progress...
Page 390: Bit Rate Register (Brr)
Section 10 Serial Communication Interface 10.2.8 Bit Rate Register (BRR) BRR7 BRR6 BRR5 BRR4 BRR3 BRR2 BRR1 BRR0 Initial value Read/Write BRR is an 8-bit register that designates the transmit/receive bit rate in accordance with the baud rate generator operating clock selected by bits CKS1 and CKS0 of the serial mode register (SMR). BRR can be read or written by the CPU at any time.
Page 391 Section 10 Serial Communication Interface Table 10.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2) φ φ φ φ 5 MHz 8 MHz 10 MHz Bit Rate Error Error Error (bit/s) 0.88 –1.36 3 0.88 1.73 0.16 –1.36 1.73 –2.34 3...
Page 392 Section 10 Serial Communication Interface Table 10.4 Relation between n and Clock SMR Setting Clock CKS1 CKS0 φ φw/2 * /φw * φ/16 φ/64 Notes: 1. φ w/2 clock in active (medium-speed/high-speed) mode and sleep mode 2. φ w clock in subactive mode and subsleep mode In subactive or subsleep mode, SCI3 can be operated when CPU clock is φw/2 only.
Page 393 Section 10 Serial Communication Interface Table 10.6 shows examples of BRR settings in synchronous mode. The values shown are for active (high-speed) mode. Table 10.6 Examples of BRR Settings for Various Bit Rates (Synchronous Mode) (1) φ φ φ φ 19.2 kHz 1 MHz 2 MHz...
Page 394 Section 10 Serial Communication Interface Table 10.6 Examples of BRR Settings for Various Bit Rates (Synchronous Mode) (2) φ φ φ φ 5 MHz 8 MHz 10 MHz Bit Rate (bit/s) Error Error Error — — — — — — 12499 —...
Page 395 Section 10 Serial Communication Interface Table 10.7 Relation between n and Clock SMR Setting Clock CKS1 CKS0 φ φ /2 * /φw * φ/16 φ/64 Notes: 1. φw/2 clock in active (medium-speed/high-speed) mode and sleep mode 2. φw clock in subactive mode and subsleep mode In subactive or subsleep mode, SCI3 can be operated when CPU clock is φw/2 only.
Page 396: Clock Stop Register 1 (Ckstpr1)
Section 10 Serial Communication Interface 10.2.9 Clock stop register 1 (CKSTPR1)   S32CKSTP ADCKSTP TGCKSTP TFCKSTP TCCKSTP TACKSTP Initial value   Read/Write CKSTPR1 is an 8-bit read/write register that performs module standby mode control for peripheral modules. Only the bits relating to SCI3 are described here. For details of the other bits, see the sections on the relevant modules.
Page 397 Section 10 Serial Communication Interface Bit 5—P4 /TXD Pin Function Switch (SPC32) This bit selects whether pin P4 /TXD is used as P4 or as TXD Bit 5 SPC32 Description Functions as P4 I/O pin (initial value) output pin * Functions as TXD Note: * Set the TE bit in SCR3 after setting this bit to 1.
Page 398: Operation
Section 10 Serial Communication Interface 10.3 Operation 10.3.1 Overview SCI3 can perform serial communication in two modes: asynchronous mode in which synchronization is provided character by character, and synchronous mode in which synchronization is provided by clock pulses. The serial mode register (SMR) is used to select asynchronous or synchronous mode and the data transfer format, as shown in table 10.8.
Page 399 Section 10 Serial Communication Interface Table 10.8 SMR Settings and Corresponding Data Transfer Formats Data Transfer Format Bit 7 Bit 6 Bit 2 Bit 5 Bit 3 Data Multiprocessor Parity Stop Bit STOP Mode Length Length Asynchronous 8-bit data No 1 bit mode 2 bits...
Page 400 Section 10 Serial Communication Interface Interrupts and Continuous Transmission/Reception SCI3 can carry out continuous reception using RXI and continuous transmission using TXI. These interrupts are shown in table 10.10. Table 10.10 Transmit/Receive Interrupts Interrupt Flags Interrupt Request Conditions Notes RDRF When serial reception is performed The RXI interrupt routine reads the normally and receive data is transferred...
Page 401 Section 10 Serial Communication Interface RSR (reception in progress) RSR↑ (reception completed, transfer) RDRF ← 1 RDRF = 0 (RXI request when RIE = 1) Figure 10.2(a) RDRF Setting and RXI Interrupt TDR (next transmit data) ↓ TSR (transmission in progress) TSR (transmission completed, transfer) TDRE ←...
Page 402: Operation In Asynchronous Mode
Section 10 Serial Communication Interface 10.3.2 Operation in Asynchronous Mode In asynchronous mode, serial communication is performed with synchronization provided character by character. A start bit indicating the start of communication and one or two stop bits indicating the end of communication are added to each character before it is sent. SCI3 has separate transmission and reception units, allowing full-duplex communication.
Page 403 Section 10 Serial Communication Interface Table 10.11 shows the 16 data transfer formats that can be set in asynchronous mode. The format is selected by the settings in the serial mode register (SMR). Table 10.11 Data Transfer Formats (Asynchronous Mode) Serial Data Transfer Format and Frame Length STOP 10 11 12...
Page 404 Section 10 Serial Communication Interface Clock Either an internal clock generated by the baud rate generator or an external clock input at the pin can be selected as the SCI3 transmit/receive clock. The selection is made by means of bit COM in SMR and bits SCE1 and CKE0 in SCR3. See table 10.9 for details on clock source selection.
Page 405 Section 10 Serial Communication Interface Figure 10.5 shows an example of a flowchart for initializing SCI3. Start Clear bits TE and RE to 0 in SCR3 Set clock selection in SCR3. Be sure to Set bits CKE1 clear the other bits to 0. If clock output and CKE0 is selected in asynchronous mode, the clock is output immediately after setting...
Page 406 Section 10 Serial Communication Interface • Transmitting Figure 10.6 shows an example of a flowchart for data transmission. This procedure should be followed for data transmission after initializing SCI3. Start Sets bit SPC32 to 1 in SPCR Read bit TDRE Read the serial status register (SSR) in SSR and check that bit TDRE is set to 1,...
Page 407 Section 10 Serial Communication Interface SCI3 operates as follows when transmitting data. SCI3 monitors bit TDRE in SSR, and when it is cleared to 0, recognizes that data has been written to TDR and transfers data from TDR to TSR. It then sets bit TDRE to 1 and starts transmitting. If bit TIE in SCR3 is set to 1 at this time, a TXI request is made.
Page 408 Section 10 Serial Communication Interface • Receiving Figure 10.8 shows an example of a flowchart for data reception. This procedure should be followed for data reception after initializing SCI3. Start Read bits OER, Read bits OER, PER, and FER in the PER, FER in SSR serial status register (SSR) to determine if there is an error.
Page 409 Section 10 Serial Communication Interface If a receive error has Start receive occurred, read bits OER, error processing PER, and FER in SSR to Overrun error identify the error, and after processing carrying out the necessary error processing, ensure OER = 1? that bits OER, PER, and FER are all cleared to 0.
Page 410 Section 10 Serial Communication Interface SCI3 operates as follows when receiving data. SCI3 monitors the communication line, and when it detects a 0 start bit, performs internal synchronization and begins reception. Reception is carried out in accordance with the relevant data transfer format in table 10.11.
Page 411: Operation In Synchronous Mode
Section 10 Serial Communication Interface Figure 10.9 shows an example of the operation when receiving in asynchronous mode. Start Receive Parity Stop Start Receive Parity Stop Mark state data data (idle state) Serial data 1 frame 1 frame RDRF RXI request RDRF 0 start bit ERI request in...
Page 412 Section 10 Serial Communication Interface Data Transfer Format The general data transfer format in asynchronous communication is shown in figure 10.10. Serial clock Serial Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 data Don't Don't...
Page 413 Section 10 Serial Communication Interface Data Transfer Operations • SCI3 initialization Data transfer on SCI3 first of all requires that SCI3 be initialized as described in section 10.3.2, 3. SCI3 initialization, and shown in figure 10.5. • Transmitting Figure 10.11 shows an example of a flowchart for data transmission. This procedure should be followed for data transmission after initializing SCI3.
Page 414 Section 10 Serial Communication Interface SCI3 operates as follows when transmitting data. SCI3 monitors bit TDRE in SSR, and when it is cleared to 0, recognizes that data has been written to TDR and transfers data from TDR to TSR. It then sets bit TDRE to 1 and starts transmitting. If bit TIE in SCR3 is set to 1 at this time, a TXI request is made.
Page 415 Section 10 Serial Communication Interface • Receiving Figure 10.13 shows an example of a flowchart for data reception. This procedure should be followed for data reception after initializing SCI3. Start Read bit OER Read bit OER in the serial status register in SSR (SSR) to determine if there is an error.
Page 416 Section 10 Serial Communication Interface SCI3 operates as follows when receiving data. SCI3 performs internal synchronization and begins reception in synchronization with the serial clock input or output. The received data is placed in RSR in LSB-to-MSB order. After the data has been received, SCI3 checks that bit RDRF is set to 0, indicating that the receive data can be transferred from RSR to RDR.
Page 417 Section 10 Serial Communication Interface • Simultaneous transmit/receive Figure 10.15 shows an example of a flowchart for a simultaneous transmit/receive operation. This procedure should be followed for simultaneous transmission/reception after initializing SCI3. Start Sets bit SPC32 to 1 in SPCR Read the serial status register (SSR) and Read bit TDRE check that bit TDRE is set to 1, then write...
Page 418: Multiprocessor Communication Function
Section 10 Serial Communication Interface Notes: 1. When switching from transmission to simultaneous transmission/reception, check that SCI3 has finished transmitting and that bits TDRE and TEND are set to 1, clear bit TE to 0, and then set bits TE and RE to 1 simultaneously. 2.
Page 419 Section 10 Serial Communication Interface Sender Communication line Receiver A Receiver B Receiver C Receiver D (ID = 01) (ID = 02) (ID = 03) (ID = 04) Serial H'01 H'AA data (MPB = 1) (MPB = 0) ID transmission cycle Data transmission cycle (specifying the receiver) (sending data to the receiver...
Page 420 Section 10 Serial Communication Interface Start Sets bit SPC32 to 1 in SPCR Read bit TDRE Read the serial status register (SSR) in SSR and check that bit TDRE is set to 1, then set bit MPBT in SSR to 0 or 1 and write transmit data to the transmit data register (TDR).
Page 421 Section 10 Serial Communication Interface SCI3 operates as follows when transmitting data. SCI3 monitors bit TDRE in SSR, and when it is cleared to 0, recognizes that data has been written to TDR and transfers data from TDR to TSR. It then sets bit TDRE to 1 and starts transmitting. If bit TIE in SCR3 is set to 1 at this time, a TXI request is made.
Page 422 Section 10 Serial Communication Interface Start Set bit MPIE to 1 in SCR3. Set bit MPIE to 1 in SCR3 Read bits OER and FER in the serial status register (SSR) to determine if there is an error. If a receive error has Read bits OER occurred, execute receive error processing.
Page 423 Section 10 Serial Communication Interface Start receive error processing Overrun error processing OER = 1? Break? FER = 1? Framing error processing Clear bits OER and FER to 0 in SSR End of receive error processing Figure 10.19 Example of Multiprocessor Data Reception Flowchart (cont) Figure 10.20 shows an example of the operation when receiving using the multiprocessor format.
Page 424 Section 10 Serial Communication Interface Start Receive Stop Start Receive data Stop Mark state data (ID1) (Data1) (idle state) Serial data 1 frame 1 frame MPIE RDRF value RXI request RDRF cleared No RXI request operation MPIE cleared to 0 RDR retains to 0 previous state...
Page 425: Interrupts
Section 10 Serial Communication Interface 10.4 Interrupts SCI3 can generate six kinds of interrupts: transmit end, transmit data empty, receive data full, and three receive error interrupts (overrun error, framing error, and parity error). These interrupts have the same vector address. The various interrupt requests are shown in table 10.13.
Page 426: Application Notes
Section 10 Serial Communication Interface 10.5 Application Notes The following points should be noted when using SCI3. 1. Relation between writes to TDR and bit TDRE Bit TDRE in the serial status register (SSR) is a status flag that indicates that data for serial transmission has not been prepared in TDR.
Page 427 Section 10 Serial Communication Interface 3. Break detection and processing When a framing error is detected, a break can be detected by reading the value of the RXD directly. In a break, the input from the RXD pin becomes all 0s, with the result that bit FER is set and bit PER may also be set.
Page 428 Section 10 Serial Communication Interface 16 clock pulses 8 clock pulses 15 0 15 0 Internal basic clock Receive data Start bit (RXD32) Synchronization sampling timing Data sampling timing Figure 10.21 Receive Data Sampling Timing in Asynchronous Mode Consequently, the receive margin in asynchronous mode can be expressed as shown in equation (1).
Page 429 Section 10 Serial Communication Interface 7. Relation between RDR reads and bit RDRF In a receive operation, SCI3 continually checks the RDRF flag. If bit RDRF is cleared to 0 when reception of one frame ends, normal data reception is completed. If bit RDRF is set to 1, this indicates that an overrun error has occurred.
Page 430 Section 10 Serial Communication Interface 8. Transmit and receive operations when making a state transition Make sure that transmit and receive operations have completely finished before carrying out state transition processing. 9. Switching SCK function If pin SCK is used as a clock output pin by SCI3 in synchronous mode and is then switched to a general input/output pin (a pin with a different function), the pin outputs a low level signal for half a system clock (φ) cycle immediately after it is switched.
Page 431: Section 11 10-Bit Pwm
Section 11 10-Bit PWM Section 11 10-Bit PWM 11.1 Overview The H8/38024 Group is provided with two on-chip 10-bit PWMs (pulse width modulators), designated PWM1 and PWM2, with identical functions. The PWMs can be used as D/A converters by connecting a low-pass filter. In this section the suffix m (m = 1 or 2) is used with register names, etc., as in PWDRLm, which denotes the PWDRL registers for each PWM.
Page 432: Block Diagram
Section 11 10-Bit PWM 11.1.2 Block Diagram Figure 11.1(1) shows a block diagram of the 10-bit PWM of the H8/38024 Group, H8/38024F- ZTAT Group, and H8/38024S Group. Figure 11.1(2) shows a block diagram of the 10-bit PWM of the H8/38124 Group. PWDRLm PWDRUm φ/2...
Page 433: Pin Configuration
Section 11 10-Bit PWM PWDRLm PWDRUm φ/2 φ/4 PWM waveform φ/8 generator φ PWCRm IECPWM PWMm (IECPWM) [Legend] m = 1 or 2 PWCRm: PWM control register PWDRLm: PWM data register L PWDRUm: PWM data register U PWMm: PWM output pin IECPWM: Event counter PWM (PWM incorporating AEC) Figure 11.1(2) Figure 11.1(1) Block Diagram of the 10-bit PWM...
Page 434: Register Configuration
Section 11 10-Bit PWM 11.1.4 Register Configuration Table 11.2 shows the register configuration of the 10-bit PWM. Table 11.2 Register Configuration Name Abbr. Initial Value Address H'FC/H'F8 * PWM1 control register PWCR1 H'FFD0 PWM1 data register U PWDRU1 H'FC H'FFD1 PWM1 data register L PWDRL1 H'00...
Page 435 Section 11 10-Bit PWM Bits 7 to 2—Reserved/Bits 7 to 3—Reserved* Bits 7 to 2 are reserved; they are always read as 1, and cannot be modified. Note: * Implemented on H8/38124 Group only. Bit 2—Output Format Select (PWCRm2)* This bit selects the format of the output from the PWMm output pin. This bit is write-only.
Page 436: Pwm Data Registers U And L (Pwdrum, Pwdrlm)
Section 11 10-Bit PWM 11.2.2 PWM Data Registers U and L (PWDRUm, PWDRLm) PWDRUm       PWDRUm1 PWDRUm0 Initial value       Read/Write PWDRLm PWDRLm7 PWDRLm6 PWDRLm5 PWDRLm4 PWDRLm3 PWDRLm2 PWDRLm1 PWDRLm0 Initial value Read/Write PWDRUm and PWDRLm form a 10-bit write-only register, with the upper 2 bits assigned to...
Page 437: Clock Stop Register 2 (Ckstpr2)
Section 11 10-Bit PWM 11.2.3 Clock Stop Register 2 (CKSTPR2) LVDCKSTP * — — PW2CKSTP AECKSTP WDCKSTP PW1CKSTP LDCKSTP Initial value Read/Write — — Note: * Bits 6 and 5 are also reserved on products other than the H8/38124 Group. CKSTPR2 is an 8-bit read/write register that performs module standby mode control for peripheral modules.
Page 438: Operation
Section 11 10-Bit PWM 11.3 Operation 11.3.1 Operation When using the 10-bit PWM, set the registers in the following sequence. 1. Set PWM1 or PWM2 in PMR9 to 1 for the PWM channel to be used, so that pin P9 /PWM1 or /PWM2 is designated as the PWM output pin, or both are designated as PWM output pins.
Page 439: Pwm Operation Modes
Section 11 10-Bit PWM 1 conversion period Figure 11.2 PWM Output Waveform 11.3.2 PWM Operation Modes PWM operation modes are shown in table 11.3. Table 11.3 PWM Operation Modes Operation Sub- Sub- Module Mode Reset Active Sleep Watch active sleep Standby Standby PWCRm...
Page 440 Section 11 10-Bit PWM Rev. 7.00 Mar 10, 2005 page 398 of 652 REJ09B0042-0700...
Page 441: Section 12 A/D Converter
Section 12 A/D Converter Section 12 A/D Converter 12.1 Overview This LSI includes on-chip a resistance-ladder-based successive-approximation analog-to-digital converter, and can convert up to 8 channels of analog input. 12.1.1 Features The A/D converter has the following features. • 10-bit resolution •...
Page 442: Block Diagram
Section 12 A/D Converter 12.1.2 Block Diagram Figure 12.1 shows a block diagram of the A/D converter. ADTRG ADSR Multiplexer Com- Control logic parator − Reference voltage ADRRH ADRRL IRRAD [Legend] AMR: A/D mode register ADSR: A/D start register ADRR: A/D result register IRRAD: A/D conversion end interrupt request flag...
Page 443: Pin Configuration
Section 12 A/D Converter 12.1.3 Pin Configuration Table 12.1 shows the A/D converter pin configuration. Table 12.1 Pin Configuration Name Abbr. Function Analog power supply Input Power supply and reference voltage of analog part Analog ground Input Ground and reference voltage of analog part Analog input 0 Input Analog input channel 0...
Page 444: Register Descriptions
Section 12 A/D Converter 12.2 Register Descriptions 12.2.1 A/D Result Registers (ADRRH, ADRRL)       ADR9 ADR8 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0       Initial value Unde- Unde- Unde- Unde- Unde- Unde-...
Page 445 Section 12 A/D Converter Bit 7—Clock Select (CKS) Bit 7 sets the A/D conversion speed. Conversion Time Bit 7 φ φ φ φ = 1 MHz φ φ φ φ = 5 MHz φ φ φ φ = 10 MHz * Conversion Period 62/φ...
Page 446: A/D Start Register (Adsr)
Section 12 A/D Converter Bits 3 to 0—Channel Select (CH3 to CH0) Bits 3 to 0 select the analog input channel. The channel selection should be made while bit ADSF is cleared to 0. Bit 3 Bit 2 Bit 1 Bit 0 Analog Input Channel No channel selected...
Page 447: Clock Stop Register 1 (Ckstpr1)
Section 12 A/D Converter Bit 7—A/D Start Flag (ADSF) Bit 7 controls and indicates the start and end of A/D conversion. Bit 7 ADSF Description Read: Indicates the completion of A/D conversion (initial value) Write: Stops A/D conversion Read: Indicates A/D conversion in progress Write: Starts A/D conversion Bits 6 to 0—Reserved Bits 6 to 0 are reserved;...
Page 448: Operation
Section 12 A/D Converter 12.3 Operation 12.3.1 A/D Conversion Operation The A/D converter operates by successive approximations, and yields its conversion result as 10- bit data. A/D conversion begins when software sets the A/D start flag (bit ADSF) to 1. Bit ADSF keeps a value of 1 during A/D conversion, and is cleared to 0 automatically when conversion is complete.
Page 449: A/D Converter Operation Modes
Section 12 A/D Converter 12.3.3 A/D Converter Operation Modes A/D converter operation modes are shown in table 12.3. Table 12.3 A/D Converter Operation Modes Operation Sub- Sub- Module Mode Reset Active Sleep Watch active sleep Standby Standby Reset Functions Functions Retained Retained Retained Retained Retained ADSR Reset Functions Functions Retained Retained Retained Retained Retained...
Page 450 Section 12 A/D Converter If ADSF is set to 1 again afterward, A/D conversion starts and steps 2 through 6 take place. Figures 12.4 and 12.5 show flow charts of procedures for using the A/D converter. Figure 12.3 Typical A/D Converter Operation Timing Rev.
Page 451 Section 12 A/D Converter Start Set A/D conversion speed and input channel Disable A/D conversion end interrupt Start A/D conversion Read ADSR ADSF = 0? Read ADRRH/ADRRL data Perform A/D conversion? Figure 12.4 Flow Chart of Procedure for Using A/D Converter (Polling by Software) Rev.
Page 452 Section 12 A/D Converter Start Set A/D conversion speed and input channel Enable A/D conversion end interrupt Start A/D conversion A/D conversion end interrupt? Clear bit IRRAD to 0 in IRR2 Read ADRRH/ADRRL data Perform A/D conversion? Figure 12.5 Flow Chart of Procedure for Using A/D Converter (Interrupts Used) Rev.
Page 453: A/D Conversion Accuracy Definitions
Section 12 A/D Converter 12.6 A/D Conversion Accuracy Definitions This LSI's A/D conversion accuracy definitions are given below. • Resolution The number of A/D converter digital output codes • Quantization error The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 12.6). •...
Page 454 Section 12 A/D Converter Digital output Ideal A/D conversion characteristic Quantization error Analog input voltage Figure 12.6 A/D Conversion Accuracy Definitions (1) Full-scale error Digital output Ideal A/D conversion characteristic Nonlinearity error Actual A/D conversion characteristic Analog Offset error input voltage Figure 12.7 A/D Conversion Accuracy Definitions (2) Rev.
Page 455: Application Notes
Section 12 A/D Converter 12.7 Application Notes 12.7.1 Permissible Signal Source Impedance This LSI’s analog input is designed such that conversion precision is guaranteed for an input signal for which the signal source impedance is 10 kΩ or less. This specification is provided to enable the A/D converter’s sample-and-hold circuit input capacitance to be charged within the sampling time;...
Page 456: Additional Usage Notes
Section 12 A/D Converter 12.7.3 Additional Usage Notes • Data in ADRRH and ADRRL should be read only when the A/D start flag (ADSF) in the A/D start register (ADSR) is cleared to 0. • Changing the digital input signal at an adjacent pin during A/D conversion may adversely affect conversion accuracy.
Page 457: Section 13 Lcd Controller/Driver
Section 13 LCD Controller/Driver Section 13 LCD Controller/Driver 13.1 Overview This LSI has an on-chip segment type LCD control circuit, LCD driver, and power supply circuit, enabling it to directly drive an LCD panel. 13.1.1 Features Features of the LCD controller/driver are given below. •...
Page 458: Block Diagram
Section 13 LCD Controller/Driver 13.1.2 Block Diagram Figures 13.1(1) and 13.1(2) show a block diagram of the LCD controller/driver. LCD drive power supply φ/256 to φ/2 Common Common φ data latch driver LPCR LCR2 Segment 32-bit shift Display timing generator driver register LCD RAM...
Page 459 Section 13 LCD Controller/Driver LCD drive power supply φ/256 to φ/2 Common Common φ w data latch driver LPCR LCR2 32-bit Segment shift Display timing generator driver register LCD RAM (16 bytes) SEGn [Legend] LPCR: LCD port control register LCR: LCD control register LCR2: LCD control register 2...
Page 460: Pin Configuration
Section 13 LCD Controller/Driver 13.1.3 Pin Configuration Table 13.1 shows the LCD controller/driver pin configuration. Table 13.1 Pin Configuration Name Abbr. Function Segment output pins to SEG Output LCD segment drive pins All pins are multiplexed as port pins (setting programmable) Common output pins to COM Output...
Page 461: Register Descriptions
Section 13 LCD Controller/Driver 13.2 Register Descriptions 13.2.1 LCD Port Control Register (LPCR)  DTS1 DTS0 SGS3 SGS2 SGS1 SGS0  Initial value Read/Write LPCR is an 8-bit read/write register which selects the duty cycle and LCD driver pin functions. Bits 7 to 5—Duty Cycle Select 1 and 0 (DTS1, DTS0), Common Function Select (CMX) The combination of DTS1 and DTS0 selects static, 1/2, 1/3, or 1/4 duty.
Page 462 Section 13 LCD Controller/Driver Bits 3 to 0—Segment Driver Select 3 to 0 (SGS3 to SGS0) Bits 3 to 0 select the segment drivers to be used. Function of Pins SEG to SEG Bit 3 Bit 2 Bit 1 Bit 0 SGS3 SGS2 SGS1...
Page 463: Lcd Control Register (Lcr)
Section 13 LCD Controller/Driver 13.2.2 LCD Control Register (LCR)  DISP CKS3 CKS2 CKS1 CKS0 Initial value  Read/Write LCR is an 8-bit read/write register which performs LCD drive power supply on/off control and display data control, and selects the frame frequency. LCR is initialized to H'80 upon reset.
Page 464 Section 13 LCD Controller/Driver Bit 4—Display Data Control (DISP) Bit 4 specifies whether the LCD RAM contents are displayed or blank data is displayed regardless of the LCD RAM contents. Bit 4 DISP Description Blank data is displayed (initial value) LCD RAM data is display Bits 3 to 0—Frame Frequency Select 3 to 0 (CKS3 to CKS0) Bits 3 to 0 select the operating clock and the frame frequency.
Page 465: Lcd Control Register 2 (Lcr2)
Section 13 LCD Controller/Driver 13.2.3 LCD Control Register 2 (LCR2) CDS3 * CDS2 * CDS1 * CDS0 * LCDAB — — — Initial value — Read/Write — — Note: * Applies to the H8/38124 Group only. On the H8/38024, H8/38024S, and H8/38024F-ZTAT Group, these bits are reserved like bit 4.
Page 466 Section 13 LCD Controller/Driver Bits 3 to 0—Removal of Split-Resistance Control These bits control whether the split-resistance is removed or connected. Note that on products other than the H8/38124 Group, these bits are reserved like bit 4. Bit 3 Bit 2 Bit 1 Bit 0 CDS3...
Page 467: Clock Stop Register 2 (Ckstpr2)
Section 13 LCD Controller/Driver 13.2.4 Clock Stop Register 2 (CKSTPR2) LVDCKSTP *   PW2CKSTP AECKSTP WDCKSTP PW1CKSTP LDCKSTP Initial value   Read/Write Note: * Bits 6 and 5 are also reserved on products other than the H8/38124 Group. CKSTPR2 is an 8-bit read/write register that performs module standby mode control for peripheral modules.
Page 468: Operation
Section 13 LCD Controller/Driver 13.3 Operation 13.3.1 Settings up to LCD Display To perform LCD display, the hardware and software related items described below must first be determined. Hardware Settings a. Using 1/2 duty When 1/2 duty is used, interconnect pins V and V as shown in figure 13.2.
Page 469 Section 13 LCD Controller/Driver Software Settings a. Duty selection Any of four duty cycles—static, 1/2 duty, 1/3 duty, or 1/4 duty—can be selected with bits DTS1 and DTS0. b. Segment selection The segment drivers to be used can be selected with bits SGS to SGS c.
Page 470: Relationship Between Lcd Ram And Display
Section 13 LCD Controller/Driver 13.3.2 Relationship between LCD RAM and Display The relationship between the LCD RAM and the display segments differs according to the duty cycle. LCD RAM maps for the different duty cycles are shown in figures 13.3 to 13.6. After setting the registers required for display, data is written to the part corresponding to the duty using the same kind of instruction as for ordinary RAM, and display is started automatically when turned on.
Page 471 Section 13 LCD Controller/Driver Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 H'F740 SEG2 SEG2 SEG2 SEG1 SEG1 SEG1 H'F74F SEG32 SEG32 SEG32 SEG31 SEG31 SEG31 COM3 COM2 COM1 COM3 COM2 COM1 Space not used for display Figure 13.4 LCD RAM Map (1/3 Duty) Rev.
Page 472 Section 13 LCD Controller/Driver Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 H'F740 SEG4 SEG4 SEG3 SEG3 SEG2 SEG2 SEG1 SEG1 Display space SEG32 SEG32 SEG31 SEG31 SEG30 SEG30 SEG29 SEG29 H'F747 Space not used for display H'F74F COM2...
Page 473 Section 13 LCD Controller/Driver 1 frame 1 frame Data Data COM1 COM1 COM2 COM2 COM3 COM3 COM4 SEGn SEGn (a) Waveform with 1/4 duty (b) Waveform with 1/3 duty 1 frame 1 frame Data Data COM1 COM1 COM2 SEGn SEGn (d) Waveform with static output (c) Waveform with 1/2 duty M: LCD alternation signal...
Page 474 Section 13 LCD Controller/Driver 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame Data Data COM1 COM1 COM2 COM2 COM3 COM3 COM4 SEGn SEGn (a) Waveform with 1/4 duty (b) Waveform with 1/3 duty 1 frame 1 frame 1 frame...
Page 475: Operation In Power-Down Modes
Section 13 LCD Controller/Driver Table 13.3 Output Levels Data Static Common output Segment output 1/2 duty Common output Segment output 1/3 duty Common output Segment output 1/4 duty Common output Segment output M: LCD alternation signal 13.3.3 Operation in Power-Down Modes This LSI the LCD controller/driver can be operated even in the power-down modes.
Page 476: Boosting The Lcd Drive Power Supply
Section 13 LCD Controller/Driver Table 13.4 Power-Down Modes and Display Operation Sub- Sub- Module Mode Reset Active Sleep Watch active sleep Standby Standby φ Stops * Clock Runs Runs Runs Stops Stops Stops Stops φw Stops * Stops * Runs Runs Runs Runs...
Page 477: Section 14 Power-On Reset And Low-Voltage Detection Circuits (H8/38124 Group Only)
Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38124 Group Only) Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38124 Group Only) 14.1 Overview This LSI can include a power-on reset circuit and low-voltage detection circuit. The low-voltage detection circuit consists of two circuits: LVDI (interrupt by low voltage detect) and LVDR (reset by low voltage detect) circuits.
Page 478: Block Diagram
Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38124 Group Only) Two pairs of detection levels for reset generation voltage are available: when only the LVDR circuit is used, or when the LVDI and LVDR circuits are both used. In addition, power supply rise/drop detection voltages and a detection voltage reference voltage may be input from an external source, allowing the detection level to be set freely by the user.
Page 479: Pin Description
Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38124 Group Only) 14.1.3 Pin Description The pins of the power-on reset circuit and low-voltage detection circuit are listed in table 14.1. Table 14.1 Pin Description Symbol Function Low-voltage detection circuit Vref Input Reference voltage input for low- reference voltage input pin...
Page 480 Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38124 Group Only) LVDCR is an 8-bit read/write register. It is used to control whether or not the low-voltage detection circuit is used, settings for external input of power supply rise and drop detection voltages, the LVDR detection level setting, enabling or disabling of resets triggered by the low- voltage detection reset circuit (LVDR), and enabling or disabling of interrupts triggered by power supply voltage drops or rises.
Page 481 Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38124 Group Only) Bit 3—LVDR Detection Level Select (LVDSEL) This bit is used to select the LVDR detection level. Select 2.3 V (typical) reset if voltage rise and drop detection interrupts are to be used. For reset detection only, Select 3.3 V (typical) reset. Bit 3 LVDSEL Description...
Page 482: Low-Voltage Detection Status Register (Lvdsr)
Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38124 Group Only) Table 14.3 shows the relationship between LVDCR settings and function selections. Refer to table 14.3 when making settings to LVDCR. Table 14.3 LVDCR Settings and Function Selections Low-Voltage Low-Voltage LVDCR Setting Value Low-Voltage Detection...
Page 483 Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38124 Group Only) Bits 6 to 4—Reserved These bits are read/write enabled reserved bits. Bit 3—Reference Voltage External Input Select (VREFSEL) This bit is used to select the reference voltage. Bit 3 VREFSEL Description The on-chip circuit is used to generate the reference voltage...
Page 484: Low-Voltage Detection Counter (Lvdcnt)
Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38124 Group Only) 14.2.3 Low-Voltage Detection Counter (LVDCNT) CNT7 CNT6 CNT5 CNT4 CNT3 CNT2 CNT1 CNT0 Initial value Read/Write LVDCNT is a read-only 8-bit up-counter. Counting begins when 1 is written to LVDE. The counter increments using φ/4 as the clock source until it overflows by switching from H'FF to H'00, at which time the OVF bit in the LVDSR register is set to 1, indicating that the on-chip reference voltage generator has stabilized.
Page 485: Operation
Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38124 Group Only) 14.3 Operation 14.3.1 Power-On Reset Circuit Figure 14.2 shows the timing of the operation of the power-on reset circuit. As the power-supply voltage rises, the capacitor which is externally connected to the pin is gradually charged via R E S the on-chip pull-up resistor (typ.
Page 486: Low-Voltage Detection Circuit
Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38124 Group Only) PWON Vpor PSS-reset signal Internal reset signal 131,072 cycles PSS counter starts Reset released Figure 14.2 Operational Timing of Power-On Reset Circuit 14.3.2 Low-Voltage Detection Circuit LVDR (Reset by Low Voltage Detect) Circuit: Figure 14.3 shows the timing of the LVDR function.
Page 487 Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38124 Group Only) Vreset LVDRmin LVDRES PSS-reset signal Internal reset signal 131,072 cycles PSS counter starts Reset released Figure 14.3 Operational Timing of LVDR Circuit LVDI (Interrupt by Low Voltage Detect) Circuit: Figure 14.4 shows the timing of LVDI functions.
Page 488 Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38124 Group Only) When the power-supply voltage does not fall below Vreset1 (typ. = 2.3 V) voltage but rises above Vint (U) (typ. = 4.0 V) voltage, the LVDI sets the signal to 1. If the LVDUE bit is 1 at L V D I N T this time, the LVDUF bit in LVDSR is set to 1 and an IRQ0 interrupt request is simultaneously generated.
Page 489 Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38124 Group Only) External power supply voltage extD input voltage extU input voltage Vexd Vreset1 LVDINTD LVDDF LVDINTU LVDUF IRQ0 interrupt IRQ0 interrupt generated generated Figure 14.5 Operational Timing of Low-Voltage Detection Interrupt Circuit (Using Pins Vref, extD, and extU) Rev.
Page 490 Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38124 Group Only) Figure 14.6 shows a usage example for the LVD function employing pins Vref, extD, and extU. LVDCR LVDRES − On-chip ladder resistor LVDINT External power − supply voltage R1 = Interrupt 517 kΩ...
Page 491 Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38124 Group Only) Resistance Value Calculation Table R (kΩ Ω Ω Ω ) R1 (kΩ Ω Ω Ω ) R2 (kΩ Ω Ω Ω ) R3 (kΩ Ω Ω Ω ) Ex. No Vref (V) Vreset1 Vint(D)
Page 492 Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38124 Group Only) Operation and Cancellation Setting Procedure Using LVDR and LVDI: Settings should be made as indicated below in order to ensure proper operation of the low voltage detection circuit or to cancel operation. Figure 14.7 shows the setting timing for low voltage detection circuit operation and cancellation.
Page 493: Section 15 Power Supply Circuit (H8/38124 Group Only)
Section 15 Power Supply Circuit (H8/38124 Group Only) Section 15 Power Supply Circuit (H8/38124 Group Only) This LSI incorporates an internal power supply step-down circuit. Use of this circuit enables the internal power supply to be fixed at a constant level of approximately 3.0 V, independently of the voltage of the power supply connected to the external V pin.
Page 494: When Not Using Internal Power Supply Step-Down Circuit
Section 15 Power Supply Circuit (H8/38124 Group Only) 15.2 When Not Using Internal Power Supply Step-Down Circuit When the internal power supply step-down circuit is not used, connect the external power supply to the CV pin and V pin, as shown in figure 15.2. The external power supply is then input directly to the internal power supply.
Page 495: Section 16 Electrical Characteristics
Section 16 Electrical Characteristics Section 16 Electrical Characteristics 16.1 H8/38024 Group ZTAT Version and Mask ROM Version Absolute Maximum Ratings Table 16.1 lists the absolute maximum ratings. Table 16.1 Absolute Maximum Ratings Item Symbol Value Unit Note Power supply voltage –0.3 to +7.0 Analog power supply voltage –0.3 to +7.0...
Page 496: H8/38024 Group Ztat Version And Mask Rom Version Electrical Characteristics
Section 16 Electrical Characteristics 16.2 H8/38024 Group ZTAT Version and Mask ROM Version Electrical Characteristics 16.2.1 Power Supply Voltage and Operating Range The power supply voltage and operating range are indicated by the shaded region in the figures. Power Supply Voltage and Oscillator Frequency Range 16.0 38.4 32.768...
Page 497 Section 16 Electrical Characteristics Power Supply Voltage and Operating Frequency Range 19.2 16.384 (0.5) 8.192 • Active (high-speed) mode • Sleep (high-speed) mode (except CPU) 4.096 Note: 1. The figure in parentheses is the minimum operating frequency when an external clock is input. When using an oscillator, the minimum operating frequency (φ) is 1 MHz.
Page 498 Section 16 Electrical Characteristics Analog Power Supply Voltage and A/D Converter Operating Range 1000 (0.5) • Active (high-speed) mode • Active (medium-speed) mode • Sleep (high-speed) mode • Sleep (medium-speed) mode = 1.8 V to 2.7 V, the operating range is limited to φ = 1.0 MHz when using an oscillator, Note: 3.
Page 499: Dc Characteristics
Section 16 Electrical Characteristics 16.2.2 DC Characteristics Table 16.2 lists the DC characteristics of the H8/38024. Table 16.2 DC Characteristics = 1.8 V to 5.5 V, AV = 1.8 V to 5.5 V, V = AV = 0.0 V, T = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range specifications), T...
Page 500 Section 16 Electrical Characteristics Values Item Symbol Applicable Pins Min Unit Test Condition Notes –0.3 — 0.2 V = 4.0 V to 5.5 V Input low R E S voltage W K P W K P –0.3 — 0.1 V Except the above I R Q I R Q...
Page 501 Section 16 Electrical Characteristics Values Item Symbol Applicable Pins Min Unit Test Condition Notes — — Output low , P1 = 4.0 V to 5.5 V voltage , P1 = 1.6 mA to P4 — — = 0.4 mA to P5 —...
Page 502 Section 16 Electrical Characteristics Values Item Symbol Applicable Pins Min Unit Test Condition Notes –I 50.0 — 300.0 µA Pull-up , P1 = 5 V, , P1 = 0 V current to P3 to P5 — 35.0 — = 2.7 V, Reference to P6 = 0 V...
Page 503 Section 16 Electrical Characteristics Values Item Symbol Applicable Pins Min Unit Test Condition Notes — µA Watch = 2.7 V, WATCH mode 32 kHz crystal current oscillator dissipation LCD not used Standby — µA 32 kHz crystal STBY mode oscillator not used current dissipation RAM data...
Page 504 Section 16 Electrical Characteristics Values Item Symbol Applicable Pins Min Unit Test Condition Notes – I All output pins — — 15.0 = 4.0 V to 5.5 V Allowable ∑ output high — — 10.0 Except the above current (total) Notes: Connect the TEST pin to V 1.
Page 505: Ac Characteristics
Section 16 Electrical Characteristics 16.2.3 AC Characteristics Table 16.3 lists the control signal timing, and tables 16.4 lists the serial interface timing of the H8/38024. Table 16.3 Control Signal Timing = 1.8 V to 5.5 V, AV = 1.8 V to 5.5 V, V = AV = 0.0 V, T = –20°C to +75°C (regular...
Page 506 Section 16 Electrical Characteristics Values Applicable Reference Item Symbol Pins Unit Test Condition Figure — — = 4.5 V to 5.5 V Figure 16.1 External clock high width — — = 2.7 V to 5.5 V — — Except the above —...
Page 507 Section 16 Electrical Characteristics Values Applicable Reference Item Symbol Pins Unit Test Condition Figure — — Figure 16.6 UD pin minimum transition width subcyc Notes: 1. Selected with SA1 and SA0 of system control register 2 (SYSCR2). 2. The figure in parentheses applies when an external clock is used. 3.
Page 508: A/D Converter Characteristics
Section 16 Electrical Characteristics 16.2.4 A/D Converter Characteristics Table 16.5 shows the A/D converter characteristics of the H8/38024. Table 16.5 A/D Converter Characteristics = 1.8 V to 5.5 V, V = AV = 0.0 V, T = –20°C to +75°C (regular specifications), = –40°C to +85°C (wide-range specifications), T = +75°C (Die) unless otherwise indicated.
Page 509 Section 16 Electrical Characteristics Values Applicable Reference Item Symbol Pins Unit Test Condition Figure — — ±3.0 Absolute = 2.7 V to 5.5 V accuracy = 2.7 V to 5.5 V — — ±6.0 = 2.0 V to 5.5 V = 2.0 V to 5.5 V —...
Page 510: Lcd Characteristics
Section 16 Electrical Characteristics 16.2.5 LCD Characteristics Table 16.6 shows the LCD characteristics. Table 16.6 LCD Characteristics = 1.8 V to 5.5 V, AV = 1.8 V to 5.5 V, V = AV = 0.0 V, T = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range specifications), T = +75°C (Die) (including...
Page 511: H8/38024 Group F-Ztat Version And H8/38024R Group F-Ztat Version Absolute Maximum Ratings
Section 16 Electrical Characteristics 16.3 H8/38024 Group F-ZTAT Version and H8/38024R Group F-ZTAT Version Absolute Maximum Ratings Table 16.7 lists the absolute maximum ratings. Table 16.7 Absolute Maximum Ratings Item Symbol Value Unit Note Power supply voltage –0.3 to +4.3 Analog power supply voltage –0.3 to +4.3 Input voltage...
Page 512: H8/38024 Group F-Ztat Version And H8/38024R Group F-Ztat Version Electrical Characteristics
Section 16 Electrical Characteristics 16.4 H8/38024 Group F-ZTAT Version and H8/38024R Group F-ZTAT Version Electrical Characteristics 16.4.1 Power Supply Voltage and Operating Range The power supply voltage and operating range are indicated by the shaded region in the figures. Power Supply Voltage and Oscillator Frequency Range 38.4 32.768 10.0...
Page 513 Section 16 Electrical Characteristics Power Supply Voltage and Operating Frequency Range 19.2 16.384 (0.5) 8.192 • Active (high-speed) mode • Sleep (high-speed) mode (except CPU) 4.096 Note: 1. The figure in parentheses is the minimum operating frequency when an external clock is input. When using an oscillator, the minimum operating frequency (φ) is 1 MHz.
Page 514 Section 16 Electrical Characteristics Analog Power Supply Voltage and A/D Converter Operating Range (0.5) • Active (high-speed) mode • Active (medium-speed) mode • Sleep (high-speed) mode • Sleep (medium-speed) mode Rev. 7.00 Mar 10, 2005 page 472 of 652 REJ09B0042-0700...
Page 515: Dc Characteristics
Section 16 Electrical Characteristics 16.4.2 DC Characteristics Table 16.8 lists the DC characteristics of the HD64F38024 and HD64F38024R. Table 16.8 DC Characteristics = 2.7 V to 3.6 V, AV = 2.7 V to 3.6 V, V = AV = 0.0 V Values Item Symbol Applicable Pins Min...
Page 516 Section 16 Electrical Characteristics Values Item Symbol Applicable Pins Min Unit Test Condition Notes –0.3 — 0.1 V Input low R E S voltage W K P W K P I R Q I R Q I R Q I R Q IRQAEC, P9 AEVL, AEVH, TMIC, TMIF,...
Page 517 Section 16 Electrical Characteristics Values Item Symbol Applicable Pins Min Unit Test Condition Notes — — = 0.4 mA Output low , P1 voltage , P1 to P3 to P4 to P5 to P6 to P7 to P8 to PA to P9 —...
Page 518 Section 16 Electrical Characteristics Values Item Symbol Applicable Pins Min Unit Test Condition Notes — — Active Active (high-speed) OPE1 mode mode current = 3 V, Max. dissipation = 2 MHz guideline = 1.1 × typ. — — Active (high-speed) mode = 3 V, Max.
Page 519 Section 16 Electrical Characteristics Values Item Symbol Applicable Pins Min Unit Test Condition Notes — — Sleep mode = 3 V, SLEEP current = 2 MHz dissipation Max. guideline = 1.1 × typ. — — = 3 V, = 4 MHz Max.
Page 520 Section 16 Electrical Characteristics Values Item Symbol Applicable Pins Min Unit Test Condition Notes — — µA Standby = 3.0 V, STBY mode = 25°C current Reference 32 kHz crystal dissipation value oscillator not used — µA 32 kHz crystal oscillator not used RAM data —...
Page 521 Section 16 Electrical Characteristics 3. Pin states during current measurement. Other LCD Power R E S Mode Internal State Pins Supply Oscillator Pins Active (high-speed) Operates Halted System clock oscillator: mode (I crystal OPE1 Active (medium- Subclock oscillator: speed) mode (I Pin X = GND OPE2...
Page 522: Ac Characteristics
Section 16 Electrical Characteristics 16.4.3 AC Characteristics Table 16.9 lists the control signal timing, and tables 16.10 lists the serial interface timing of the H8/38024F. Table 16.9 Control Signal Timing = 2.7 V to 3.6 V, AV = 2.7 V to 3.6 V, V = AV = 0.0 V Values...
Page 523 Section 16 Electrical Characteristics Values Applicable Reference Pins Figure Item Symbol Unit Test Condition External clock high — — Figure 16.1 width — 15.26 — µs 13.02 External clock low — — Figure 16.1 width — 15.26 — µs 13.02 External clock rise —...
Page 524 Section 16 Electrical Characteristics Table 16.10 Serial Interface (SCI3) Timing = 2.7 V to 3.6 V, AV = 2.7 V to 3.6 V, V = AV = 0.0 V Values Reference Item Symbol Unit Test Conditions Figure Input clock Asynchronous —...
Page 525: A/D Converter Characteristics
Section 16 Electrical Characteristics 16.4.4 A/D Converter Characteristics Table 16.11 shows the A/D converter characteristics of the H8/38024F. Table 16.11 A/D Converter Characteristics = 2.7 V to 3.6 V, V = AV = 0.0 V Values Applicable Reference Item Symbol Pins Unit Test Condition...
Page 526: Lcd Characteristics
Section 16 Electrical Characteristics 16.4.5 LCD Characteristics Table 16.12 shows the LCD characteristics. Table 16.12 LCD Characteristics = 2.7 V to 3.6 V, AV = 2.7 V to 3.6 V, V = AV = 0.0 V Values Applicable Test Reference Item Symbol Pins...
Page 527: Flash Memory Characteristics
Section 16 Electrical Characteristics 16.4.6 Flash Memory Characteristics Table 16.13 lists the flash memory characteristics. Table 16.13 Flash Memory Characteristics = 2.7 V to 3.6 V, V = AV = 0.0 V, V = 2.7 V to 3.6 V (operating voltage range in reading), V = 3.0 V to 3.6 V (operating voltage range in programming/erasing), T = –20 to...
Page 528 Section 16 Electrical Characteristics Notes: 1. Make the time settings in accordance with the program/erase algorithms. The programming time for 128 bytes. (Indicates the total time for which the P bit in flash memory control register 1 (FLMCR1) is set. The program-verify time is not included.) The time required to erase one block.
Page 529: H8/38024S Group Mask Rom Version Absolute Maximum Ratings
Section 16 Electrical Characteristics 16.5 H8/38024S Group Mask ROM Version Absolute Maximum Ratings Table 16.14 lists the absolute maximum ratings. Table 16.14 Absolute Maximum Ratings Item Symbol Value Unit Note Power supply voltage –0.3 to +4.3 Analog power supply voltage –0.3 to +4.3 Input voltage Ports other than Port B...
Page 530: H8/38024S Group Mask Rom Version Electrical Characteristics
Section 16 Electrical Characteristics 16.6 H8/38024S Group Mask ROM Version Electrical Characteristics 16.6.1 Power Supply Voltage and Operating Range The power supply voltage and operating range are indicated by the shaded region in the figures. Power Supply Voltage and Oscillator Frequency Range 38.4 32.768 10.0...
Page 531 Section 16 Electrical Characteristics Power Supply Voltage and Operating Frequency Range 19.2 16.384 (0.5) 8.192 • Active (high-speed) mode • Sleep (high-speed) mode (except CPU) 4.096 Note: 1. The figure in parentheses is the minimum operating frequency when an external clock is input. When using an oscillator, the minimum operating frequency (φ) is 1 MHz.
Page 532 Section 16 Electrical Characteristics Analog power Supply Voltage and A/D Converter Operating Range (0.5) • Active (high-speed) mode • Active (medium-speed) mode • Sleep (high-speed) mode • Sleep (medium-speed) mode Rev. 7.00 Mar 10, 2005 page 490 of 652 REJ09B0042-0700...
Page 533: Dc Characteristics
Section 16 Electrical Characteristics 16.6.2 DC Characteristics Table 16.15 lists the DC characteristics of the H8/38024S. Table 16.15 DC Characteristics = 1.8 V to 3.6 V, AV = 1.8 V to 3.6 V, V = AV = 0.0 V Values Item Symbol Applicable Pins Min Unit Test Condition...
Page 534 Section 16 Electrical Characteristics Values Item Symbol Applicable Pins Min Unit Test Condition Notes –0.3 — 0.1 V Input low R E S voltage W K P W K P I R Q I R Q I R Q I R Q IRQAEC, AEVL, AEVH, TMIC, TMIF, TMIG,...
Page 535 Section 16 Electrical Characteristics Values Item Symbol Applicable Pins Min Unit Test Condition Notes — — = 0.4 mA Output low , P1 voltage , P1 to P3 to P4 to P5 to P6 to P7 to P8 to PA to P9 —...
Page 536 Section 16 Electrical Characteristics Values Item Symbol Applicable Pins Min Unit Test Condition Notes — — Active Active (high-speed) OPE1 mode mode current = 1.8 V, Max. dissipation = 1 MHz guideline = 1.1 × typ. — — Active (high-speed) mode = 3 V, Max.
Page 537 Section 16 Electrical Characteristics Values Item Symbol Applicable Pins Min Unit Test Condition Notes — — Active Active (medium- OPE2 mode speed) mode current = 3 V, Max. dissipation = 4 MHz guideline φ /128 = 1.1 × typ. — Active (medium- speed) mode = 3 V,...
Page 538 Section 16 Electrical Characteristics Values Item Symbol Applicable Pins Min Unit Test Condition Notes — — µA Subactive = 1.8 V, mode LCD on 32 kHz current crystal oscillator Reference dissipation (φ =φ value — — µA = 2.7 V, LCD on 32 kHz crystal oscillator Reference...
Page 539 Section 16 Electrical Characteristics Values Item Symbol Applicable Pins Min Unit Test Condition Notes — — µA Standby = 1.8 V, STBY mode = 25°C current 32 kHz crystal Reference dissipation oscillator not used value — — µA = 3.0 V, = 25°C 32 kHz crystal Reference...
Page 540 Section 16 Electrical Characteristics Notes: Connect the TEST pin to V 1. Pin states during current measurement. Other LCD Power R E S Mode Internal State Pins Supply Oscillator Pins Active (high-speed) Operates Halted System clock oscillator: mode (I crystal OPE1 Active (medium- Subclock oscillator:...
Page 541: Ac Characteristics
Section 16 Electrical Characteristics 16.6.3 AC Characteristics Table 16.16 lists the control signal timing, and tables 16.10 lists the serial interface timing of the H8/38024S. Table 16.16 Control Signal Timing = 1.8 V to 3.6 V, AV = 1.8 V to 3.6 V, V = AV = 0.0 V Values...
Page 542 Section 16 Electrical Characteristics Values Applicable Reference Pins Figure Item Symbol Unit Test Condition , OSC — µs Oscillation Ceramic oscillator Figure 16.9 stabilization time = 2.2 V to 3.6 V — — µs Ceramic oscillator Except the above — Crystal oscillator = 2.7 V to 3.6 V —...
Page 543 Section 16 Electrical Characteristics Values Applicable Reference Pins Figure Item Symbol Unit Test Condition Input pin high width t — — Figure 16.3 I R Q I R Q I R Q I R Q subcyc IRQAEC, W K P W K P TMIC, TMIF, TMIG,...
Page 544 Section 16 Electrical Characteristics Table 16.17 Serial Interface (SCI3) Timing = 1.8 V to 3.6 V, AV = 1.8 V to 3.6 V, V = AV = 0.0 V Values Reference Item Symbol Unit Test Conditions Figure Input clock Asynchronous —...
Page 545: A/D Converter Characteristics
Section 16 Electrical Characteristics 16.6.4 A/D Converter Characteristics Table 16.18 shows the A/D converter characteristics of the H8/38024S. Table 16.18 A/D Converter Characteristics = 1.8 V to 3.6 V, V = AV = 0.0 V Values Applicable Reference Pins Figure Item Symbol Unit...
Page 546: Lcd Characteristics
Section 16 Electrical Characteristics 3. AI is the current at reset and in standby, watch, subactive, and subsleep modes STOP2 while the A/D converter is idle. 4. Conversion time: 62 µs. 16.6.5 LCD Characteristics Table 16.19 shows the LCD characteristics. Table 16.19 LCD Characteristics = 1.8 V to 3.6 V, AV = 1.8 V to 3.6 V, V...
Page 547: Absolute Maximum Ratings Of H8/38124 Group F-Ztat Version And Mask Rom Version
Section 16 Electrical Characteristics 16.7 Absolute Maximum Ratings of H8/38124 Group F-ZTAT Version and Mask ROM Version Table 16.20 lists the absolute maximum ratings. Table 16.20 Absolute Maximum Ratings Item Symbol Value Unit Note Power supply voltage –0.3 to +7.0 –0.3 to +4.3 Analog power supply voltage –0.3 to +7.0...
Page 548: Electrical Characteristics Of H8/38124 Group F-Ztat Version And Mask Rom Version
Section 16 Electrical Characteristics 16.8 Electrical Characteristics of H8/38124 Group F-ZTAT Version and Mask ROM Version 16.8.1 Power Supply Voltage and Operating Ranges Power Supply Voltage and Oscillation Frequency Range (System Clock Oscillator Selected) 20.0 32.768 • Active (high-speed) mode •...
Page 549 Section 16 Electrical Characteristics Power Supply Voltage and Operating Frequency Range (System Clock Oscillator Selected) 10.0 16.384 8.192 • Active (high-speed) mode • Sleep (high-speed) mode (except CPU) 4.096 • Subactive mode 1250 • Subsleep mode (except CPU) • Watch mode (except CPU) 15.625 •...
Page 550 Section 16 Electrical Characteristics Power Supply Voltage and Operating Frequency Range (On-Chip Oscillator Selected) 16.384 8.192 4.096 0.35 • Active (high-speed) mode • Sleep (high-speed) mode (except CPU) • Subactive mode • Subsleep mode (except CPU) • Watch mode (except CPU) 6.25 •...
Page 551 Section 16 Electrical Characteristics Analog Power Supply Voltage and A/D Converter Operating Range (System Clock Oscillator Selected) 10.0 1000 • Active (high-speed) mode • Active (medium-speed) mode • Sleep (high-speed) mode • Sleep (medium-speed) mode Analog Power Supply Voltage and A/D Converter Operating Range (On-Chip Oscillator Selected) 6.25 0.35...
Page 552: Dc Characteristics
Section 16 Electrical Characteristics 16.8.2 DC Characteristics Table 16.21 lists the DC characteristics. Table 16.21 DC Characteristics = 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = AV = 0.0 V, unless otherwise specified Values Item Symbol Applicable Pins...
Page 553 Section 16 Electrical Characteristics Values Item Symbol Applicable Pins Unit Test Condition Notes × 0.2 Input low – 0.3 — = 4.0 V to 5.5 V R E S voltage W K P W K P I R Q I R Q I R Q I R Q IRQAEC, P9...
Page 554 Section 16 Electrical Characteristics Values Item Symbol Applicable Pins Unit Test Condition Notes Output low , P1 , P1 — — = 4.0 V to 5.5 V voltage to P4 = 1.6 mA to P5 to P6 — — = 0.4 mA to P7 to P8 to PA...
Page 555 Section 16 Electrical Characteristics Values Item Symbol Applicable Pins Unit Test Condition Notes Input All input pins — — 15.0 f = 1 MHz, capaci- except power = 0.0 V, tance supply pin = 25°C Active — — Active (high-speed) OPE1 mode mode...
Page 556 Section 16 Electrical Characteristics Values Item Symbol Applicable Pins Unit Test Condition Notes Active — — Active (medium- OPE2 mode speed) mode Approx. current = 2.7 V, max. value = 1.1 × consump- = 2 MHz, φ tion /128 Typ. —...
Page 557 Section 16 Electrical Characteristics Values Item Symbol Applicable Pins Unit Test Condition Notes Sleep — — = 2.7 V, SLEEP = 2 MHz mode Approx. current max. value = 1.1 × consump- tion Typ. — — Approx. max. value = 1.1 × Typ.
Page 558 Section 16 Electrical Characteristics Values Item Symbol Applicable Pins Unit Test Condition Notes Subsleep — µA = 2.7 V, SUBSP mode LCD on, current 32-kHz crystal consump- resonator used = φ tion (φ Watch — — µA = 2.7 V, WATCH mode = 25°C,...
Page 559 Section 16 Electrical Characteristics Values Applicable Test Item Symbol Pins Unit Condition Notes Allowable output low Output pins — — = 4.0 V to current (per pin) 5.5 V except ports 3 and 9 Port 3 — — 10.0 = 4.0 V to 5.5 V Output pins —...
Page 560 Section 16 Electrical Characteristics 3. Pin states when current consumption is measured LCD Power Mode Internal State Other Pins Supply Oscillator Pins R E S Active (high-speed) Only CPU operates Stops System clock: mode (I crystal resonator OPE1 Active (medium- Subclock: speed) mode (I Pin X...
Page 561: Ac Characteristics
Section 16 Electrical Characteristics 16.8.3 AC Characteristics Table 16.22 lists the control signal timing and table 16.23 lists the serial interface timing. Table 16.22 Control Signal Timing = 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = AV = 0.0 V, unless otherwise specified Values...
Page 562 When designing systems, make sure to give due consideration to the SPEC range. Please contact a Renesas sales or support representative for actual performance data on the product.
Page 563: A/D Converter Characteristics
Section 16 Electrical Characteristics 16.8.4 A/D Converter Characteristics Table 16.24 shows the A/D converter characteristics. Table 16.24 A/D Converter Characteristics = 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = AV = 0.0 V, unless otherwise specified Values Applicable Test...
Page 564: Lcd Characteristics
Section 16 Electrical Characteristics 16.8.5 LCD Characteristics Table 16.25 shows the LCD characteristics. Table 16.25 LCD Characteristics = 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = AV = 0.0 V, unless otherwise specified Values Applicable Reference Pins...
Page 565: Flash Memory Characteristics
Section 16 Electrical Characteristics 16.8.6 Flash Memory Characteristics Table 16.26 Flash Memory Characteristics Condition: = 2.7 V to 5.5 V, V = AV = 0.0 V, V = 2.7 V to 5.5 V (range of operating voltage when reading), V = 3.0 V to 5.5 V (range of operating voltage when programming/erasing), T = –20°C to +75°C (range of operating temperature...
Page 566 Section 16 Electrical Characteristics Values Test Item Symbol Unit Conditions Erase Wait time after — — µs SWE-bit setting * Wait time after — — µs ESU-bit setting * Wait time after — E-bit setting * α Wait time after —...
Page 567: Power Supply Voltage Detection Circuit Characteristics
Section 16 Electrical Characteristics 16.8.7 Power Supply Voltage Detection Circuit Characteristics Table 16.27 Power Supply Voltage Detection Circuit Characteristics (1) = 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = AV = 0.0 V, unless otherwise specified Rated Values Test Conditions Item...
Page 568 Section 16 Electrical Characteristics Table 16.29 Power Supply Voltage Detection Circuit Characteristics (3) Using on-chip reference voltage and detect voltage external input (VREFSEL = 0, VINTDSEL and VINTUSEL = 1) Rated Values Item Symbol Unit Test Condition extD/extU interrupt Vexd 0.80 1.20 1.60...
Page 569 Section 16 Electrical Characteristics Table 16.30 Power Supply Voltage Detection Circuit Characteristics (4) Using external reference voltage and ladder resistor (VREFSEL = 1, VINTDSEL = VINTUSEL = Rated Values Test Item Symbol Unit Condition Vint(D) * – Power supply drop 3.08 * (Vref1 0.1) 3.08 * Vref1...
Page 570: Power-On Reset Circuit Characteristics
Section 16 Electrical Characteristics Table 16. 31 Power Supply Voltage Detection Circuit Characteristics (5) Using external reference voltage and detect voltage external input (VREFSEL = VINTDSEL = VINTUSEL = 1) Rated Values Item Symbol Unit Test Condition Comparator detection Vcdl —...
Page 571: Watchdog Timer Characteristics
Section 16 Electrical Characteristics 16.8.9 Watchdog Timer Characteristics Table 16.33 Watchdog Timer Characteristics = 2.7 V to 5.5 V, V = AV = 0.0 V, unless otherwise specified Rated Values Applicable Test Item Symbol Pins Unit Note Condition On-chip oscillator —...
Page 572 Section 16 Electrical Characteristics Figure 16.2 Low Width R E S , IRQ , IRQ , IRQ TMIC, TMIF, TMIG, ADTRG, WKP to WKP IRQAEC, AEVL, AEVH Figure 16.3 Input Timing SCKW scyc Figure 16.4 SCK3 Input Clock Timing Rev. 7.00 Mar 10, 2005 page 530 of 652 REJ09B0042-0700...
Page 573 Section 16 Electrical Characteristics scyc or V or V (transmit data) (receive data) Note: * Output timing reference levels Output high = 1/2Vcc + 0.2 V Output low = 0.8 V Load conditions are shown in figure 16.7. Figure 16.5 SCI3 Synchronous Mode Input/Output Timing Figure 16.6 UD Pin Minimum Transition Width Timing Rev.
Page 574: Output Load Circuit
Section 16 Electrical Characteristics 16.10 Output Load Circuit 2.4 kΩ Output pin 30 pF 12 kΩ Figure 16.7 Output Load Condition 16.11 Resonator Equivalent Circuit Crystal Resonator Parameters Ceramic Resonator Parameters Frequency Frequency 4.193 (MHz) (MHz) 100 Ω 100 Ω 30 Ω...
Page 575: Usage Note
Section 16 Electrical Characteristics Crystal Resonator Parameters Ceramic Resonator Parameters (1) (Manufacturer's Publicly Released Values) (Manufacturer's Publicly Released Values) Frequency Frequency Manufacturer Manufacturer (MHz) (MHz) 100 Ω 18.3 Ω Murata Manufacturing Co., Ltd. (max) Nihon Dempa Kogyo Co., Ltd. (max) (max) 16 pF (max)
Page 576 Section 16 Electrical Characteristics Rev. 7.00 Mar 10, 2005 page 534 of 652 REJ09B0042-0700...
Page 577: Appendix A Cpu Instruction Set
Appendix A CPU Instruction Set Appendix A CPU Instruction Set Instructions Operation Notation Rd8/16 General register (destination) (8 or 16 bits) Rs8/16 General register (source) (8 or 16 bits) Rn8/16 General register (8 or 16 bits) Condition code register N (negative) flag in CCR Z (zero) flag in CCR V (overflow) flag in CCR C (carry) flag in CCR...
Page 578 Appendix A CPU Instruction Set Table A.1 lists the H8/300L CPU instruction set. Table A.1 Instruction Set Addressing Mode/ Instruction Length (bytes) Condition Code Mnemonic Operation I H N Z V C B #xx:8 → Rd8   0  2 MOV.B #xx:8, Rd B Rs8 →...
Page 579 Appendix A CPU Instruction Set Addressing Mode/ Instruction Length (bytes) Condition Code Mnemonic Operation I H N Z V C B Rd8+#xx:8 → Rd8  ADD.B #xx:8, Rd B Rd8+Rs8 → Rd8  ADD.B Rs, Rd W Rd16+Rs16 → Rd16 ...
Page 580 Appendix A CPU Instruction Set Addressing Mode/ Instruction Length (bytes) Condition Code Mnemonic Operation I H N Z V C B Rd8 × Rs8 → Rd16       14 MULXU.B Rs, Rd B Rd16÷Rs8 → Rd16 ...
Page 581 Appendix A CPU Instruction Set Addressing Mode/ Instruction Length (bytes) Condition Code Mnemonic Operation I H N Z V C   ROTL.B Rd   ROTR.B Rd B (#xx:3 of Rd8) ← 1       2 BSET #xx:3, Rd B (#xx:3 of @Rd16) ←...
Page 582 Appendix A CPU Instruction Set Addressing Mode/ Instruction Length (bytes) Condition Code Mnemonic Operation I H N Z V C B (#xx:3 of Rd8) → Z      2 BTST #xx:3, Rd B (#xx:3 of @Rd16) → Z ...
Page 583 Appendix A CPU Instruction Set Addressing Mode/ Instruction Length (bytes) Condition Code Branching Mnemonic Operation Condition I H N Z V C B C∨(#xx:3 of @aa:8) → C      BIOR #xx:3, @aa:8 B C⊕(#xx:3 of Rd8) → C ...
Page 584 Appendix A CPU Instruction Set Addressing Mode/ Instruction Length (bytes) Condition Code Mnemonic Operation I H N Z V C  SP−2 → SP       6 JSR @Rn PC → @SP PC ← Rn16  SP−2 → SP ...
Page 585: Operation Code Map
Appendix A CPU Instruction Set Operation Code Map Table A.2 is an operation code map. It shows the operation codes contained in the first byte of the instruction code (bits 15 to 8 of the first instruction word). Instruction when first bit of byte 2 (bit 7 of first instruction word) is 0. Instruction when first bit of byte 2 (bit 7 of first instruction word) is 1.
Page 586 Appendix A CPU Instruction Set Table A.2 Operation Code Map Rev. 7.00 Mar 10, 2005 page 544 of 652 REJ09B0042-0700...
Page 587: Number Of Execution States
Appendix A CPU Instruction Set Number of Execution States The tables here can be used to calculate the number of states required for instruction execution. Table A.4 indicates the number of states required for each cycle (instruction fetch, read/write, etc.), and table A.3 indicates the number of cycles of each type occurring in each instruction. The total number of states required for execution of an instruction can be calculated from these two tables as follows: Execution states = I •...
Page 588 Appendix A CPU Instruction Set Table A.4 Number of Cycles in Each Instruction Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation N Instruction Mnemonic ADD.B #xx:8, Rd ADD.B Rs, Rd ADD.W Rs, Rd ADDS ADDS.W #1, Rd ADDS.W #2, Rd...
Page 589 Appendix A CPU Instruction Set Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic BILD BILD #xx:3, Rd BILD #xx:3, @Rd BILD #xx:3, @aa:8 BIOR BIOR #xx:3, Rd BIOR #xx:3, @Rd BIOR #xx:3, @aa:8 BIST BIST #xx:3, Rd BIST #xx:3, @Rd...
Page 590 Appendix A CPU Instruction Set Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic BTST BTST Rn, @aa:8 BXOR BXOR #xx:3, Rd BXOR #xx:3, @Rd BXOR #xx:3, @aa:8 CMP. B #xx:8, Rd CMP.
Page 591 Appendix A CPU Instruction Set Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic MOV.W Rs, @Rd MOV.W Rs, @(d:16, Rd) MOV.W Rs, @–Rd MOV.W Rs, @aa:16 MULXU MULXU.B Rs, Rd NEG.B Rd NOT.B Rd OR.B #xx:8, Rd OR.B Rs, Rd...
Page 592: Appendix B Internal I/O Registers
Appendix B Internal I/O Registers Appendix B Internal I/O Registers Addresses Upper Address: H'F0 Bit Names Lower Register Address Name Module Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 H'20 FLMCR1 —...
Page 593 Appendix B Internal I/O Registers Upper Address: H'FF Bit Names Lower Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name H'80 H'81 H'82 H'83 H'84 H'85 H'86 LVDCR LVDE —...
Page 594 Appendix B Internal I/O Registers Upper Address: H'FF Bit Names Lower Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name H'A0 H'A1 H'A2 H'A3 H'A4 H'A5 H'A6 H'A7 H'A8 STOP CKS1...
Page 595 Appendix B Internal I/O Registers Upper Address: H'FF Bit Names Lower Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name H'C0 LPCR DTS1 DTS0 — SGS3 SGS2 SGS1 SGS0 LCD controller/ driver...
Page 596 Appendix B Internal I/O Registers Upper Address: H'FF Bit Names Lower Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name H'E0 PUCR1 PUCR17 PUCR16 — PUCR14 PUCR13 — —...
Page 597: Functions
Appendix B Internal I/O Registers Functions Address to which the register is mapped. Register name When displayed with two-digit number, this indicates the lower address, Register acronym and the upper address is HFF. Name of on-chip supporting module H'B6 Timer F TCRFTimer Control Register F Bit numbers Initial bit values...
Page 598 Appendix B Internal I/O Registers FLMCR1—Flash Memory Control Register 1 H'F020 Flash Memory  Initial value  Read/Write Program 0 Program mode cleared (initial value) 1 Transition to program mode [Setting condition] When SWE = 1 and PSU = 1 Erase 0 Erase mode cleared (initial value) 1 Transition to erase mode...
Page 599 Appendix B Internal I/O Registers FLMCR2—Flash Memory Control Register 2 H'F021 Flash Memory        FLER Initial value        Read/Write Flash memory error Note: A write to FLMCR2 is prohibited. FLPWCR—Flash Memory Power Control Register H'F022 Flash Memory...
Page 600 Appendix B Internal I/O Registers EBR—Erase Block Register H'F023 Flash Memory    Initial value    Read/Write Blocks 4 to 0 0 When a block of EB4 to EB0 is not selected (initial value) 1 When a block of EB4 to EB0 is selected Note: Set the bit of EBR to H'00 when erasing.
Page 601 Appendix B Internal I/O Registers LVDCR—Low-Voltage Detection Control Register H'86 LVDC Note: This register is implemented on the H8/38124 Group only.  LVDE VINTDSEL VINTUSEL LVDSEL LVDRE LVDDE LVDUE Initial value Read/Write Voltage Rise Interrupt Enable 0 Voltage rise interrupt requests disabled (initial value) 1 Voltage rise interrupt requests enabled Voltage Drop Interrupt Enable 0 Voltage drop interrupt requests disabled (initial value)
Page 602 Appendix B Internal I/O Registers LVDSR—Low-Voltage Detection Status Register H'87 LVDC Note: This register is implemented on the H8/38124 Group only.     VREFSEL LVDDF LVDUF Initial value Read/Write LVD Power Supply Voltage Rise Flag 0 [Clearing condition] (initial v alue) When 0 is written after reading 1 1 [Setting condition]...
Page 603 Appendix B Internal I/O Registers ECPWCRH—Event Counter PWM Compare Register H H'8C ECPWCRH7 ECPWCRH6 ECPWCRH5 ECPWCRH4 ECPWCRH3 ECPWCRH2 ECPWCRH1 ECPWCRH0 Initial value Sets event counter PWM waveform conversion period ECPWCRL—Event Counter PWM Compare Register L H'8D ECPWCRL7 ECPWCRL6 ECPWCRL5 ECPWCRL4 ECPWCRL3 ECPWCRL2 ECPWCRL1 ECPWCRL0 Initial value Sets event counter PWM waveform conversion period ECPWDRH—Event Counter PWM Data Register H...
Page 604 Appendix B Internal I/O Registers WEGR—Wakeup Edge Select Register H'90 System Control WKEGS7 WKEGS6 WKEGS5 WKEGS4 WKEGS3 WKEGS2 WKEGS1 WKEGS0 Initial value Read/Write WKPn Edge Selected WKPn pin falling edge detected WKPn pin rising edge detected (n = 7 to 0) Rev.
Page 605 Appendix B Internal I/O Registers SPCR—Serial Port Control Register H'91 SCI3      SPC32 SCINV3 SCINV2    Initial value   Read/Write Pin Input Data Inversion Switch input data is not inverted input data is inverted Pin Output Data Inversion Switch output data is not inverted output data is inverted...
Page 606 Appendix B Internal I/O Registers AEGSR—Input Pin Edge Select Register H'92  AHEGS1 AHEGS0 ALEGS1 ALEGS0 AIEGS1 AIEGS0 ECPWME Initial value Read/Write Event Counter PWM Enable/Disable, IRQAEC Select/Deselect AEC PWM halted, IRQAEC selected AEC PWM operation enabled, IRQAEC deselected IRQAEC Edge Select Bit 3 Bit 2 Description...
Page 607 Appendix B Internal I/O Registers ECCR—Event Counter Control Register H'94  ACKH1 ACKH0 ACKL1 ACKL0 PWCK2 PWCK1 PWCK0 Initial value Read/Write Event Counter PWM Clock Select Bit 3 Bit 2 Bit 1 Description PWCK2 PWCK1 PWCK0 φ/2 φ/4 φ/8 φ/16 φ/32 φ/64 *: Don't care...
Page 608 Appendix B Internal I/O Registers ECCSR—Event Counter Control/Status Register H'95  CUEH CUEL CRCH CRCL Initial value Read/Write Counter Reset Control L ECL is reset ECL reset is cleared and count-up function is enabled Counter Reset Control H ECH is reset ECH reset is cleared and count-up function is enabled Count-up Enable L...
Page 609 Appendix B Internal I/O Registers ECH—Event Counter H H'96 ECH7 ECH6 ECH5 ECH4 ECH3 ECH2 ECH1 ECH0 Initial value Read/Write Count value Note: ECH and ECL can also be used as the upper and lower halves, respectively, of a 16-bit timer counter (EC).
Page 610 Appendix B Internal I/O Registers SMR—Serial Mode Register H'A8 SCI3 STOP CKS1 CKS0 Initial value Read/Write Clock Select φ clock φ w /2 clock φ/16 clock φ/64 clock Multiprocessor Mode Multiprocessor communication function disabled Multiprocessor communication function enabled Stop Bit Length 1 stop bit 2 stop bits Parity Mode...
Page 611 Appendix B Internal I/O Registers BRR—Bit Rate Register H'A9 SCI3 BRR7 BRR6 BRR5 BRR4 BRR3 BRR2 BRR1 BRR0 Initial value Read/Write Serial transmit/receive bit rate Rev. 7.00 Mar 10, 2005 page 569 of 652 REJ09B0042-0700...
Page 612 Appendix B Internal I/O Registers SCR3—Serial Control Register 3 H'AA SCI3 MPIE TEIE CKE1 CKE0 Initial value Read/Write Clock Enable Description Bit 1 Bit 0 CKE1 CKE0 Communication Mode Clock Source Pin Function Asynchronous Internal clock I/O port Synchronous Internal clock Serial clock output Asynchronous Internal clock...
Page 613 Appendix B Internal I/O Registers TDR—Transmit Data Register H'AB SCI3 TDR7 TDR6 TDR5 TDR4 TDR3 TDR2 TDR1 TDR0 Initial value Read/Write Data for transfer to TSR Rev. 7.00 Mar 10, 2005 page 571 of 652 REJ09B0042-0700...
Page 614 Appendix B Internal I/O Registers SSR—Serial Status Register H'AC SCI3 TDRE RDRF TEND MPBR MPBT Initial value R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * Read/Write Multiprocessor Bit Transfer A 0 multiprocessor bit is transmitted A 1 multiprocessor bit is transmitted Multiprocessor Bit Receive Data in which the multiprocessor bit is 0 has been received Data in which the multiprocessor bit is 1 has been received...
Page 615 Appendix B Internal I/O Registers RDR—Receive Data Register H'AD SCI3 RDR7 RDR6 RDR5 RDR4 RDR3 RDR2 RDR1 RDR0 Initial value Read/Write Serial receiving data are stored TMA—Timer Mode Register A H'B0 Timer A     TMA3 TMA2 TMA1 TMA0 ...
Page 616 Appendix B Internal I/O Registers TCA—Timer Counter A H'B1 Timer A TCA7 TCA6 TCA5 TCA4 TCA3 TCA2 TCA1 TCA0 Initial value Read/Write Count value Rev. 7.00 Mar 10, 2005 page 574 of 652 REJ09B0042-0700...
Page 617 Appendix B Internal I/O Registers TCSRW—Timer Control/Status Register W H'B2 Watchdog Timer B6WI TCWE B4WI TCSRWE B2WI WDON BOWI WRST Initial value R/(W) * R/(W) * R/(W) * R/(W) * Read/Write Watchdog Timer Reset Clearing conditions: Reset by RES pin When TCSRWE = 1, and 0 is written in both B0WI and WRST Setting condition:...
Page 618 Appendix B Internal I/O Registers TCW—Timer Counter W H'B3 Watchdog Timer TCW7 TCW6 TCW5 TCW4 TCW3 TCW2 TCW1 TCW0 Initial value Read/Write Count value TMC—Timer Mode Register C H'B4 Timer C   TMC7 TMC6 TMC5 TMC2 TMC1 TMC0 Initial value ...
Page 619 Appendix B Internal I/O Registers TCC—Timer Counter C H'B5 Timer C TCC7 TCC6 TCC5 TCC4 TCC3 TCC2 TCC1 TCC0 Initial value Read/Write Count value Note: TCC is allocated to the same address as TLC. In a read, the TCC value is returned. TLC—Timer Load Register C H'B5 Timer C...
Page 620 Appendix B Internal I/O Registers TCRF—Timer Control Register F H'B6 Timer F TOLH CKSH2 CKSH1 CKSH0 TOLL CKSL2 CKSL1 CKSL0 Initial value Read/Write Clock Select L Except Counting on external event (TMIF) for 11 rising/falling edge Do not specify this combination Internal clock φ/32 Internal clock φ/16 Internal clock φ/4...
Page 621 Appendix B Internal I/O Registers TCSRF—Timer Control/Status Register F H'B7 Timer F OVFH CMFH OVIEH CCLRH OVFL CMFL OVIEL CCLRL Initial value R/(W) * R/(W) * R/(W) * R/(W) * Read/Write Counter Clear L TCFL clearing by compare match is disabled TCFL clearing by compare match is enabled Timer Overflow Interrupt Enable L TCFL overflow interrupt request is disabled...
Page 622 Appendix B Internal I/O Registers TCFH—8-Bit Timer Counter FH H'B8 Timer F TCFH7 TCFH6 TCFH5 TCFH4 TCFH3 TCFH2 TCFH1 TCFH0 Initial value Read/Write Count value Note: TCFH and TCFL can also be used as the upper and lower halves, respectively, of a 16-bit timer counter (TCF).
Page 623 Appendix B Internal I/O Registers OCRFL—Output Compare Register FL H'BB Timer F OCRFL7 OCRFL6 OCRFL5 OCRFL4 OCRFL3 OCRFL2 OCRFL1 OCRFL0 Initial value Read/Write Note: OCRFH and OCRFL can also be used as the upper and lower halves, respectively, of a 16-bit output compare register (OCRF). Rev.
Page 624 Appendix B Internal I/O Registers TMG—Timer Mode Register G H'BC Timer G OVFH OVFL OVIE IIEGS CCLR1 CCLR0 CKS1 CKS0 Initial value R/(W) * R/(W) * Read/Write Clock Select Internal clock: counting on φ/64 1 Internal clock: counting on φ/32 1 0 Internal clock: counting on φ/2 1 Internal clock: counting on φ...
Page 625 Appendix B Internal I/O Registers ICRGF—Input Capture Register GF H'BD Timer G ICRGF7 ICRGF6 ICRGF5 ICRGF4 ICRGF3 ICRGF2 ICRGF1 ICRGF0 Initial value Read/Write Stores TCG value at falling edge of input capture signal ICRGR—Input Capture Register GR H'BE Timer G ICRGR7 ICRGR6 ICRGR5...
Page 626 Appendix B Internal I/O Registers LPCR—LCD Port Control Register H'C0 LCD Controller/Driver  DTS1 DTS0 SGS3 SGS2 SGS1 SGS0  Initial value Read/Write Segment Driver Select Function of Pins SEG to SEG Bit 3 Bit 2 Bit 1 Bit 0 Note SGS3 SGS2...
Page 627 Appendix B Internal I/O Registers LCR—LCD Control Register H'C1 LCD Controller/Driver  DISP CKS3 CKS2 CKS1 CKS0 Initial value  Read/Write Frame Frequency Select Bit 1 Bit 1 Bit 3 Bit 2 Operating Clock CKS2 CKS3 CKS1 CKS0 φ w φ...
Page 628 Appendix B Internal I/O Registers LCR2—LCD Control Register 2 H'C2    LCDAB CDS3 CDS2 CDS1 CDS0  Initial value   Read/Write A Waveform/B Waveform Switching Control 0 Drive using A waveform 1 Drive using B waveform Removal of Split-Resistance Control CDS3 CDS2 CDS1...
Page 629 Appendix B Internal I/O Registers AMR—A/D Mode Register H'C6 A/D Converter   TRGE Initial value   Read/Write Channel Select Bit 3 Bit 2 Bit 1 Bit 0 Analog Input Channel No channel selected Do not specify this combination *: Don't care External Trigger Select 0 Disables start of A/D conversion by external trigger...
Page 630 Appendix B Internal I/O Registers ADRRH—A/D Result Register H H'C4 A/D Converter ADRRL—A/D Result Register L H'C5 ADRRH ADR9 ADR8 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Read/Write A/D conversion result ADRRL ...
Page 631 Appendix B Internal I/O Registers PMR1—Port Mode Register 1 H'C8 I/O Port      IRQ3 IRQ4 TMIG    Initial value   Read/Write /TMIG Pin Function Switch 0 Functions as P1 I/O pin 1 Functions as TMIG input pin /IRQ /ADTRG Pin Function Switch 0 Functions as P1...
Page 632 Appendix B Internal I/O Registers PMR2—Port Mode Register 2 H'C9 I/O Port     POF1 WDCKS IRQ0 Initial value     Read/Write /IRQ0 Pin Function Switch 0 Functions as P4 I/O pin 1 Functions as IRQ input pin TMIG Noise Canceller Select 0 Noise cancellation function not used...
Page 633 Appendix B Internal I/O Registers PMR3—Port Mode Register 3 H'CA I/O Port    AEVL AEVH TMOFH TMOFL    Initial value Read/Write /UD Pin Function Switch 0 Functions as P3 I/O pin 1 Functions as UD input pin /TMOFL Pin Function Switch 0 Functions as P3 I/O pin...
Page 634 Appendix B Internal I/O Registers PMR5—Port Mode Register 5 H'CC I/O Port Initial value Read/Write /WKP /SEG Pin Function Switch 0 Functions as P5 I/O pin 1 Functions as WKP input pin (n = 7 to 0) PWCR2—PWM2 Control Register H'CD 10-Bit PWM ...
Page 635 Appendix B Internal I/O Registers PWDRU2—PWM2 Data Register U H'CE 10-Bit PWM       PWDRU21 PWDRU20 Initial value       Read/Write Upper 2 bits of PWM2 waveform generation data PWDRL2—PWM2 Data Register L H'CF 10-Bit PWM PWDRL27...
Page 636 Appendix B Internal I/O Registers PWCR1—PWM1 Control Register H'D0 10-Bit PWM      PWCR12 PWCR11 PWCR10 Initial value      Read/Write Clock Select 0 The input clock is φ (tφ * = 1/φ) The conversion period is 512/φ, with a minimum modulation width of 1/2φ The input clock is φ/2 (tφ...
Page 637 Appendix B Internal I/O Registers PWDRU1—PWM1 Data Register U H'D1 10-Bit PWM       PWDRU11 PWDRU10 Initial value       Read/Write Upper 2 bits of data for generating PWM1 waveform PWDRL1—PWM1 Data Register L H'D2 10-Bit PWM PWDRL17...
Page 638 Appendix B Internal I/O Registers PDR4—Port Data Register 4 H'D7 I/O Ports     Initial value     Read/Write Data for port 4 pins Reads P4 state PDR5—Port Data Register 5 H'D8 I/O Ports Initial value Read/Write Data for port 5 pins PDR6—Port Data Register 6...
Page 639 Appendix B Internal I/O Registers PDR8—Port Data Register 8 H'DB I/O Ports Initial value Read/Write Data for port 8 pins PDR9—Port Data Register 9 H'DC I/O Ports   Initial value   Read/Write Data for port 9 pins PDRA—Port Data Register A H'DD I/O Ports ...
Page 640 Appendix B Internal I/O Registers PUCR1—Port Pull-Up Control Register 1 H'E0 I/O Ports     PUCR1 PUCR1 PUCR1 PUCR1     Initial value Read/Write Port 1 Input Pull-up MOS Control Input pull-up MOS is off Input pull-up MOS is on Note: When the PCR1 specification is 0.
Page 641 Appendix B Internal I/O Registers PUCR5—Port Pull-Up Control Register 5 H'E2 I/O Ports PUCR5 PUCR5 PUCR5 PUCR5 PUCR5 PUCR5 PUCR5 PUCR5 Initial value Read/Write Port 5 Input Pull-up MOS Control Input pull-up MOS is off Input pull-up MOS is on Note: When the PCR5 specification is 0.
Page 642 Appendix B Internal I/O Registers PCR1—Port Control Register 1 H'E4 I/O Ports     PCR1 PCR1 PCR1 PCR1     Initial value Read/Write Port 1 Input/Output Select 0 Input pin 1 Output pin Note: * PCR1 is not equipped with H8/38124 Group.
Page 643 Appendix B Internal I/O Registers PCR5—Port Control Register 5 H'E8 I/O Ports PCR5 PCR5 PCR5 PCR5 PCR5 PCR5 PCR5 PCR5 Initial value Read/Write Port 5 Input/Output Select 0 Input pin 1 Output pin PCR6—Port Control Register 6 H'E9 I/O Ports PCR6 PCR6 PCR6...
Page 644 Appendix B Internal I/O Registers PCR8—Port Control Register 8 H'EB I/O Ports PCR8 PCR8 PCR8 PCR8 PCR8 PCR8 PCR8 PCR8 Initial value Read/Write Port 8 Input/Output Select 0 Input pin 1 Output pin PMR9—Port Mode Register 9 H'EC I/O Ports PIOFF/...
Page 645 Appendix B Internal I/O Registers PCRA—Port Control Register A H'ED I/O Ports     PCRA PCRA PCRA PCRA Initial value     Read/Write Port A Input/Output Select 0 Input pin 1 Output pin PMRB—Port Mode Register B H'EE I/O Ports ...
Page 646 Appendix B Internal I/O Registers SYSCR1—System Control Register 1 H'F0 System Control  SSBY STS2 STS1 STS0 LSON Initial value  Read/Write Active (medium-speed) Mode Clock Select φ φ φ φ /128 Low Speed on Flag 0 The CPU operates on the system clock (φ) 1 The CPU operates on the subclock (φ...
Page 647 Appendix B Internal I/O Registers SYSCR2—System Control Register 2 H'F1 System Control    NESEL DTON MSON Initial value    Read/Write Subactive Mode Clock Select φ φ φ Medium Speed on Flag *: Don't care 0 Operates in active (high-speed) mode 1 Operates in active (medium-speed) mode Direct Transfer on Flag 0 •...
Page 648 Appendix B Internal I/O Registers IEGR—IRQ Edge Select Register H'F2 System Control     IEG4 IEG3 IEG1 IEG0  Initial value    Read/Write Edge Select 0 Falling edge of IRQ pin input is detected Rising edge of IRQ pin input is detected Edge Select 0 Falling edge of IRQ...
Page 649 Appendix B Internal I/O Registers IENR1—Interrupt Enable Register 1 H'F3 System Control  IENTA IENWP IEN4 IEN3 IENEC2 IEN1 IEN0  Initial value Read/Write to IRQ Interrupt Enable 0 Disables IRQ to IRQ interrupt, requests Enables IRQ to IRQ interrupt requests IRQAEC Interrupt Enable 0 Disables IRQAEC interrupt requests Enables IRQAEC interrupt requests...
Page 650 Appendix B Internal I/O Registers IENR2—Interrupt Enable Register 2 H'F4 System Control  IENDT IENAD IENTG IENTFH IENTFL IENTC IENEC  Initial value Read/Write Asynchronous Event Counter Interrupt Enable 0 Disables asynchronous event counter interrupt requests 1 Enables asynchronous event counter interrupt requests Timer C Interrupt Enable 0 Disables timer C interrupt requests...
Page 651 Appendix B Internal I/O Registers OSCCR—Clock Pulse Generator Control Register H'F5 Clock Pulse Generator Note: This register is implemented on the H8/38124 Group only.      SUBSTP IRQAECF OSCF   Initial value Read/Write OSC Flag 0 Operation using system clock oscillator (on-chip oscillator stopped) 1 Operation using on-chip oscillator (system clock oscillator stopped) IRQAEC Flag 0 IRQAEC pin set to GND during resets...
Page 652 Appendix B Internal I/O Registers IRR1—Interrupt Request Register 1 H'F6 System Control   IRRTA IRRI4 IRRI3 IRREC2 IRRI1 IRRI0  Initial value R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * R/(W) *  Read/Write IRQ1 and IRQ0 Interrupt Request Flags 0 Clearing condition: When IRRIn = 1, it is cleared by writing 0 1 Setting condition:...
Page 653 Appendix B Internal I/O Registers IRR2—Interrupt Request Register 2 H'F7 System Control  IRRDT IRRAD IRRTG IRRTFH IRRTFL IRRTC IRREC  Initial value R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * Read/Write Asynchronous Event Counter Interrupt Request Flag 0 Clearing condition: When IRREC = 1, it is cleared by writing 0 1 Setting condition:...
Page 654 Appendix B Internal I/O Registers TMW—Timer Mode Register W H'F8 Watchdog Timer Note: This register is implemented on the H8/38124 Group only.     CKS3 CKS2 CKS1 CKS0 Initial value     Read/Write Internal Clock Select CDS3 CDS2 CDS1...
Page 655 Appendix B Internal I/O Registers IWPR—Wakeup Interrupt Request Register H'F9 System Control IWPF7 IWPF6 IWPF5 IWPF4 IWPF3 IWPF2 IWPF1 IWPF0 Initial value R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * Read/Write Wakeup Interrupt Request Register 0 Clearing condition: When IWPFn = 1, it is cleared by writing 0 1 Setting condition:...
Page 656 Appendix B Internal I/O Registers CKSTPR1—Clock Stop Register 1 H'FA System Control   S32CKSTP ADCKSTP TGCKSTP TFCKSTP TCCKSTP TACKSTP Initial value   Read/Write Timer A Module Standby Mode Control 0 Timer A is set to module standby mode Timer A module standby mode is cleared Timer C Module Standby Mode Control 0 Timer C is set to module standby mode...
Page 657 Appendix B Internal I/O Registers CKSTPR2—Clock Stop Register 2 H'FB System Control   LVDCKSTP* PW2CKSTP AECKSTP WDCKSTP PW1CKSTP LDCKSTP Initial value   Read/Write LCD Module Standby Mode Control 0 LCD is set to module standby mode LCD module standby mode is cleared PWM1 Module Standby Mode Control 0 PWM1 is set to module standby mode PWM1 module standby mode is cleared...
Page 658: Appendix C I/O Port Block Diagrams
Appendix C I/O Port Block Diagrams Appendix C I/O Port Block Diagrams Block Diagrams of Port 1 SBY (low level during reset and in standby mode) PUCR1 PMR1 PDR1 PCR1 PDR1: Port data register 1 PCR1: Port control register 1 PMR1: Port mode register 1 PUCR1:...
Page 659 Appendix C I/O Port Block Diagrams SBY (low level during reset and in standby mode) PUCR1 PMR1 PDR1 PCR1 PDR1: Port data register 1 PCR1: Port control register 1 PMR1: Port mode register 1 PUCR1: Port pull-up control register 1 Figure C.1(b) Port 1 Block Diagram (Pin P1 , Products other than H8/38124 Group) Rev.
Page 660 Appendix C I/O Port Block Diagrams PUCR1 PMR1 PDR1 PCR1 Timer G module TMIG PDR1: Port data register 1 PCR1: Port control register 1 PMR1: Port mode register 1 PUCR1: Port pull-up control register 1 Figure C.1(c) Port 1 Block Diagram (Pin P1 Rev.
Page 661: Block Diagrams Of Port 3
Appendix C I/O Port Block Diagrams Block Diagrams of Port 3 PUCR3 PMR3 PDR3 PCR3 AEC module AEVH(P3 AEVL(P3 PDR3: Port data register 3 PCR3: Port control register 3 PMR3: Port mode register 3 PUCR3: Port pull-up control register 3 n = 7 and 6 Figure C.2(a) Port 3 Block Diagram (Pins P3 and P3...
Page 662 Appendix C I/O Port Block Diagrams PUCR3 PMR2 PDR3 PCR3 PDR3: Port data register 3 PCR3: Port control register 3 PUCR3: Port pull-up control register 3 PMR2 Port mode register 2 Figure C.2(b) Port 3 Block Diagram (Pin P3 Rev. 7.00 Mar 10, 2005 page 620 of 652 REJ09B0042-0700...
Page 663 Appendix C I/O Port Block Diagrams PUCR3 PDR3 PCR3 PDR3: Port data register 3 PCR3: Port control register 3 n = 4 and 3 Figure C.2(c) Port 3 Block Diagram (Pins P3 and P3 Rev. 7.00 Mar 10, 2005 page 621 of 652 REJ09B0042-0700...
Page 664 Appendix C I/O Port Block Diagrams TMOFH (P3 TMOFL (P3 PUCR3 PMR3 PDR3 PCR3 PDR3: Port data register 3 PCR3: Port control register 3 PMR3: Port mode register 3 PUCR3: Port pull-up control register 3 n = 2 and 1 Figure C.2(d) Port 3 Block Diagram (Pins P3 and P3 Rev.
Page 665 Appendix C I/O Port Block Diagrams PUCR3 PMR3 PDR3 PCR3 Timer C module PDR3: Port data register 3 PCR3: Port control register 3 PMR3: Port mode register 3 PUCR3: Port pull-up control register 3 Figure C.2(e) Port 3 Block Diagram (Pin P3 Rev.
Page 666: Block Diagrams Of Port 4
Appendix C I/O Port Block Diagrams Block Diagrams of Port 4 PMR2 PMR2: Port mode register 2 Figure C.3(a) Port 4 Block Diagram (Pin P4 Rev. 7.00 Mar 10, 2005 page 624 of 652 REJ09B0042-0700...
Page 667 Appendix C I/O Port Block Diagrams SCINV3 SPC32 SCI3 module TXD32 PDR4 PCR4 PDR4: Port data register 4 PCR4: Port control register 4 Figure C.3(b) Port 4 Block Diagram (Pin P4 Rev. 7.00 Mar 10, 2005 page 625 of 652 REJ09B0042-0700...
Page 668 Appendix C I/O Port Block Diagrams SCI3 module RE32 RXD32 PDR4 PCR4 SCINV2 PDR4: Port data register 4 PCR4: Port control register 4 Figure C.3(c) Port 4 Block Diagram (Pin P4 Rev. 7.00 Mar 10, 2005 page 626 of 652 REJ09B0042-0700...
Page 669 Appendix C I/O Port Block Diagrams SCI3 module SCKIE32 SCKOE32 SCKO32 SCKI32 PDR4 PCR4 PDR4: Port data register 4 PCR4: Port control register 4 Figure C.3(d) Port 4 Block Diagram (Pin P4 Rev. 7.00 Mar 10, 2005 page 627 of 652 REJ09B0042-0700...
Page 670: Block Diagram Of Port 5
Appendix C I/O Port Block Diagrams Block Diagram of Port 5 SBY * PUCR5 PMR5 PDR5 PCR5 PDR5: Port data register 5 PCR5: Port control register 5 PMR5: Port mode register 5 Note: * The value of SBY is fixed at 1 in the HD64F38024. PUCR5: Port pull-up control register 5 n = 7 to 0 Figure C.4 Port 5 Block Diagram...
Page 671: Block Diagram Of Port 6
Appendix C I/O Port Block Diagrams Block Diagram of Port 6 PUCR6 PDR6 PCR6 PDR6: Port data register 6 PCR6: Port control register 6 PUCR6: Port pull-up control register 6 n = 7 to 0 Figure C.5 Port 6 Block Diagram Rev.
Page 672: Block Diagram Of Port 7
Appendix C I/O Port Block Diagrams Block Diagram of Port 7 PDR7 PCR7 PDR7: Port data register 7 PCR7: Port control register 7 n = 7 to 0 Figure C.6 Port 7 Block Diagram Rev. 7.00 Mar 10, 2005 page 630 of 652 REJ09B0042-0700...
Page 673: Block Diagram Of Port 8
Appendix C I/O Port Block Diagrams Block Diagram of Port 8 PDR8 PCR8 PDR8: Port data register 8 PCR8: Port control register 8 n = 7 to 0 Figure C.7 Port 8 Block Diagram Rev. 7.00 Mar 10, 2005 page 631 of 652 REJ09B0042-0700...
Page 674: Block Diagrams Of Port 9
Appendix C I/O Port Block Diagrams Block Diagrams of Port 9 PWM module PMR9 PDR9 PDR9: Port data register 9 n = 1 and 0 Figure C.8(a) Port 9 Block Diagram (Pins P9 and P9 PDR9 PDR9: Port data register 9 n = 5 to 2 Figure C.8(b) Port 9 Block Diagram (Pins P9 to P9...
Page 675 Appendix C I/O Port Block Diagrams PDR9 LVD module VREFSEL Vref PDR9: Port data register 9 Figure C.8(c) Port 9 Block Diagram (Pins P9 , H8/38124 Group only) Rev. 7.00 Mar 10, 2005 page 633 of 652 REJ09B0042-0700...
Page 676: Block Diagram Of Port A
Appendix C I/O Port Block Diagrams Block Diagram of Port A PDRA PCRA PDRA: Port data register A PCRA: Port control register A n = 3 to 0 Figure C.9 Port A Block Diagram Rev. 7.00 Mar 10, 2005 page 634 of 652 REJ09B0042-0700...
Page 677: Block Diagrams Of Port B
Appendix C I/O Port Block Diagrams C.10 Block Diagrams of Port B Internal data bus A/D module AMR3 to AMR0 n = 7 to 0 Figure C.10(a) Port B Block Diagram Rev. 7.00 Mar 10, 2005 page 635 of 652 REJ09B0042-0700...
Page 678 Appendix C I/O Port Block Diagrams Internal data bus A/D module AMR3 to AMR0 LVD module VINTDSEL extD Figure C.10(b) Port B Block Diagram (Pin PB , H8/38124 Group only) Rev. 7.00 Mar 10, 2005 page 636 of 652 REJ09B0042-0700...
Page 679 Appendix C I/O Port Block Diagrams Internal data bus A/D module AMR3 to AMR0 LVD module VINTUSEL extU Figure C.10(c) Port B Block Diagram (Pin PB , H8/38124 Group only) Rev. 7.00 Mar 10, 2005 page 637 of 652 REJ09B0042-0700...
Page 680: Appendix D Port States In The Different Processing States
Appendix D Port States in the Different Processing States Appendix D Port States in the Different Processing States Table D.1 Port States Overview Port Reset Sleep Subsleep Standby Watch Subactive Active High Retained Retained High Retained Functions Functions impedance * impedance High Retained...
Page 681: Appendix E List Of Product Codes
Appendix E List of Product Codes Appendix E List of Product Codes Table E.1 H8/38024 Group Product Code Lineup Package Product Type Product Code Mark Code (Package Code) H8/38024 H8/38024 Mask ROM Regular HD64338024H HD64338024(***)H 80-pin QFP (FP-80A) Group versions specifications HD64338024F HD64338024(***)F...
Page 682 Appendix E List of Product Codes Package Product Type Product Code Mark Code (Package Code) H8/38024 H8/38023 Mask ROM Regular HD64338023H HD64338023(***)H 80-pin QFP (FP-80A) Group versions specifications HD64338023F HD64338023(***)F 80-pin QFP (FP-80B) HD64338023W HD64338023(***)W 80-pin TQFP (TFP-80C) HCD64338023 — Wide-range HD64338023D HD64338023(***)H...
Page 683 Appendix E List of Product Codes Package Product Type Product Code Mark Code (Package Code) H8/38024S H8/38024S Mask ROM Regular HD64338024SH HD64338024(***)H 80-pin QFP (FP-80A) Group versions specifications HD64338024SW HD64338024(***)W 80-pin TQFP (TFP-80C) HD64338024SLPV 338024S(***)LPV 85-pin TFLGA (TLP-85V) HCD64338024S — Wide-range HD64338024SD HD64338024(***)H...
Page 684 Appendix E List of Product Codes Package Product Type Product Code Mark Code (Package Code) H8/38124 H8/38124 F-ZTAT Regular HD64F38124H F38124H 80-pin QFP (FP-80A) Group versions specifications HD64F38124W F38124W 80-pin TQFP (TFP-80C) Wide-range HD64F38124HW F38124H 80-pin QFP (FP-80A) specifications HD64F38124WW F38124W 80-pin TQFP (TFP-80C) Mask ROM...
Page 685: Appendix F Package Dimensions
Appendix F Package Dimensions Appendix F Package Dimensions Dimensional drawings of the H8/38024 Group, H8/38024S Group, and H8/38124 Group packages FP-80A, FP-80B, and TFP-80C are shown in figures F.1, F.2, and F.3 below. 17.2 ± 0.3 Unit: mm * 0.32 ± 0.08 0.12 M 0.30 ±...
Page 686 Appendix F Package Dimensions 24.8 ± 0.4 Unit: mm * 0.37 ± 0.08 0.15 M 0.35 ± 0.06 0° − 10° 1.2 ± 0.2 0.15 Package Code FP-80B  JEDEC * Dimension including the plating thickness  JEITA Mass (reference value) 1.7 g Base material dimension Figure F.2 FP-80B Package Dimensions...
Page 687 Appendix F Package Dimensions 14.0 ± 0.2 Unit: mm 0.22 ± 0.05 0.10 0.20 ± 0.04 1.25 0° − 8° 0.5 ± 0.1 0.10 Package Code TFP-80C  JEDEC * Dimension including the plating thickness JEITA Conforms Base material dimension Mass (reference value) 0.4 g Figure F.3 TFP-80C Package Dimensions...
Page 688 Appendix F Package Dimensions Unit: mm 0.20 C A 4 × 0.15 0.65 0.575 85 × φ0.35 ± 0.05 φ0.08 0.10 C (Flatness of land portion) Figure F.4 TLP-85V Package Dimensions Rev. 7.00 Mar 10, 2005 page 646 of 652 REJ09B0042-0700...
Page 689: Appendix G Specifications Of Chip Form
Appendix G Specifications of Chip Form Appendix G Specifications of Chip Form The specifications of the chip form of the HCD64338024, HCD64338023, HCD64338022, HCD64338021, and HCD64338020 are shown in figure G.1. The specifications of the chip form of the HCD64F38024 and HCD64F38024R are shown in figure G.2. The specifications of the chip form of the HCD64338024S, HCD64338023S, HCD64338022S, HCD64338021S, and HCD64338020S are shown in figure G.3.
Page 690 Appendix G Specifications of Chip Form X-direction: 2.91 ± 0.05 Y-direction: 2.91 ± 0.05 X-direction: 2.91 ± 0.25 Maximum plain Y-direction: 2.91 ± 0.25 Unit: mm Figure G.3 Chip Sectional Figure of the HCD64338024S, HCD64338023S, HCD64338022S, HCD64338021S, and HCD64338020S Rev. 7.00 Mar 10, 2005 page 648 of 652 REJ09B0042-0700...
Page 691 Appendix H Form of Bonding Pads Appendix H Form of Bonding Pads The form of the bonding pads for the HCD64338024, HCD64338023, HCD64338022, HCD64338021, HCD64338020, HCD64F38024, HCD64F38024R, HCD64338024S, HCD64338023S, HCD64338022S, HCD64338021S, and HCD64338020S is shown in figure H.1. Bonding area Metal layer 72 mm 5 mm...
Page 692 Appendix I Specifications of Chip Tray Appendix I Specifications of Chip Tray The specifications of the chip tray for the HCD64338024, HCD64338023, HCD64338022, HCD64338021, and HCD64338020 are shown in figure I.1. The specifications of the chip tray for the HCD64F38024 and HCD64F38024R are shown in figure I.2. The specifications of the chip tray for the HCD64338024S, HCD64338023S, HCD64338022S, HCD64338021S, and HCD64338020S are shown in figure I.3.
Page 693 Appendix I Specifications of Chip Tray Chip direction Chip Type name 3.84 Chip tray name DAINIPPON-INK-&-CHEMICALS-INC. Type: CT015 Carved code: TCT45-060P 4.5 ± 0.05 6.2 ± 0.1 6.9 ± 0.1 Unit: mm X-X' cross section Figure I.2 Specifications of Chip Tray for the HCD64F38024 and HCD64F38024R Rev.
Page 694 Appendix I Specifications of Chip Tray Chip direction Type name Chip 2.91 Chip tray name DAINIPPON-INK-&-CHEMICALS-INC. Type: CT022 Carved code: TCT036036-060 3.6 ± 0.05 4.48 ± 0.1 5.34 ± 0.1 Unit: mm X-X' cross section Figure I.3 Specifications of Chip Tray for the HCD64338024S, HCD64338023S, HCD64338022S, HCD64338021S, and HCD64338020S Rev.
Page 695 Publication Date: 1st Edition, November 2000 Rev.7.00, March 10, 2005 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Technical Documentation & Information Department Renesas Kodaira Semiconductor Co., Ltd. © 2005. Renesas Technology Corp. All rights reserved. Printed in Japan.
Page 696 Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan http://www.renesas.com RENESAS SALES OFFICES Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.
Page 697 H8/38024, H8/38024S, H8/38024R, H8/38124 Group Hardware Manual...

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Renesas H8 Series Hardware Manual

Section 1 Overview

Section 2 CPU

Section 3 Exception Handling

Section 4 Clock Pulse Generators

Section 5 Power-Down Modes

Section 6 ROM

Section 7 RAM

Section 8 I/O Ports

Section 9 Timers

Section 10 Serial Communication Interface

Section 11 10-Bit PWM

Section 12 A/D Converter

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Summary of Contents for Renesas H8 Series