Dram Interface Bus Timing - Renesas H8/3067 Series User Manual

21.3.4

DRAM Interface Bus Timing

DRAM interface bus timing is shown as follows:
• DRAM bus timing: read and write access
Figure 21.17 shows the timing of the read and write access.
• DRAM bus timing: CAS before RAS refresh
Figure 21.18 shows the timing of the CAS before RAS refresh.
• DRAM bus timing: self-refresh
Figure 21.19 shows the timing of the self-refresh.
Section 21 Electrical Characteristics
Rev. 4.00 Jan 26, 2006 page 745 of 938
REJ09B0276-0400