System Control Register (Syscr) - Renesas H8S/2437 Hardware Manual

3.2.2

System Control Register (SYSCR)

SYSCR selects saturating calculation for the MAC instruction, and controls reset source monitor,
Ram address space, and on-chip flash memory control.
Bit Bit Name Initial Value
7 MACS

6 to 4
3 XRST
2 FLASHE

1
0 RAME
R/W
0 R/W
All 0 R/W
1 R
0 R/W
0 R/W
1 R/W
Descriptions
MAC Saturation
Selects either saturating or non-saturating calculation
for the MAC instruction.
0: Non-saturating calculation for MAC instruction
1: Saturating calculation for MAC instruction
Reserved
The initial value should not be changed.
External Reset
Indicates reset source. Reset occurs as external reset
input or watchdog timer overflow.
0: Generated by watchdog timer overflow
1: Generated by external reset
Flash Memory Control Register Enable
Controls CPU access to the flash memory control
registers (FCCS, FPCS, FECS, FKEY, FMATS, and
FTDAR).
0: Flash memory control registers are not selected
1: Flash memory control registers are selected
Reserved
The initial value should not be changed.
RAM Enable
Enables or disables the on-chip RAM. The RAME bit
is initialized when the reset status is released.
0: On-chip RAM is disabled
1: On-chip RAM is enabled
Rev. 1.00, 09/03, page 53 of 704