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Section 9 16-Bit Timer
• Input capture signal timing
Input capture on the rising edge, falling edge, or both edges can be selected by settings in
TIOR. Figure 9.23 shows the timing when the rising edge is selected. The pulse width of the
input capture signal must be at least 1.5 system clocks for single-edge capture, and 2.5 system
clocks for capture of both edges.
φ
Input-capture input
Input capture signal
TCNT
GRA, GRB
Rev. 4.00 Jan 26, 2006 page 370 of 938
REJ09B0276-0400
Figure 9.23 Input Capture Signal Timing
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