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Section 4 Exception Handling
4.5
Stack Status after Exception Handling
Figure 4.6 shows the stack after completion of trap instruction exception handling and interrupt
exception handling.
SP–4
SP–3
SP–2
SP–1
SP (ER7) →
Before exception handling
SP–4
SP–3
SP–2
SP–1
SP (ER7) →
Before exception handling
Legend
PCE:
Bits 23 to 16 of program counter (PC)
PCH:
Bits 15 to 8 of program counter (PC)
PCL:
Bits 7 to 0 of program counter (PC)
CCR:
Condition code register
SP:
Stack pointer
Notes:
*
Ignored at return.
1.
PC indicates the address of the first instruction that will be executed after return.
2.
Registers must be saved in word or longword size at even addresses.
Figure 4.6 Stack after Completion of Exception Handling
Rev. 4.00 Jan 26, 2006 page 88 of 938
REJ09B0276-0400
SP (ER7)
SP+1
SP+2
SP+3
Stack area
SP+4
Pushed on stack
a. Normal mode
SP (ER7)
SP+1
SP+2
SP+3
SP+4
Stack area
Pushed on stack
b. Advanced mode
→
CCR
CCR
*
PC
H
PC
L
After exception handling
→
CCR
PC
E
PC
H
PC
L
After exception handling
Even address
Even address
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