Renesas H8/3067 Series User Manual page 250

Section 7 DMA Controller
DTCRB
Bit 7
DTME
Initial value 0
Read/Write R/W
Data transfer master enable
Enables or disables data
transfer, together with
the DTE bit, and is cleared
to 0 by an interrupt
DTCRB is initialized to H'00 by a reset and in standby mode.
Bit 7—Data Transfer Master Enable (DTME): Together with the DTE bit in DTCRA, this bit
enables or disables data transfer. When the DTME and DTE bits are both set to 1, the channel is
enabled. When an NMI interrupt occurs DTME is cleared to 0, suspending the transfer so that the
CPU can use the bus. The suspended transfer resumes when DTME is set to 1 again. For further
information on operation in block transfer mode, see section 7.6.6, NMI Interrupts and Block
Transfer Mode.
DTME is set to 1 by reading the register while DTME = 0, then writing 1.
Bit 7
DTME Description
0 Data transfer is disabled (DTME is cleared to 0 when an NMI interrupt
occurs)
1 Data transfer is enabled
Bit 6—Reserved: Although reserved, this bit can be written and read.
Rev. 4.00 Jan 26, 2006 page 226 of 938
REJ09B0276-0400
6 5
Ñ DAID
0 0
R/W R/W
Reserved bit
Destination address
increment/decrement
Destination address
increment/decrement enable
These bits select whether
the destination address
register (MARB) is incremented,
decremented, or held fixed
during the data transfer
4 3
DAIDE TMS DTS2B
0 0
R/W R/W R/W
Transfer mode select
Selects whether the
block area is the source
or destination in block
transfer mode
2 1 0
DTS1B DTS0B
0 0 0
R/W R/W
Data transfer select
2B to 0B
These bits select the data
transfer activation source
(Initial value)