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Section 7 DMA Controller
7.4.5
Normal Mode
In normal mode the A and B channels are combined. One byte or word is transferred per request.
A designated number of these transfers are executed. Addresses are specified in MARA and
MARB. Table 7.9 indicates the register functions in I/O mode.
Table 7.9
Register Functions in Normal Mode
Register
23
MARA
23
MARB
15
ETCRA
Legend
MARA: Memory address register A
MARB: Memory address register B
ETCRA: Execute transfer count register A
The source and destination addresses are both 24-bit addresses. MARA specifies the source
address. MARB specifies the destination address. MARA and MARB can be independently
incremented, decremented, or held fixed as data is transferred.
The transfer count is specified as a 16-bit value in ETCRA. The ETCRA value is decremented by
1 at each transfer. When the ETCRA value reaches H'0000, the DTE bit is cleared and the transfer
ends. If the DTIE bit is set to 1, a CPU interrupt is requested at this time. The maximum transfer
count is 65,536, obtained by setting ETCRA to H'0000.
Rev. 4.00 Jan 26, 2006 page 240 of 938
REJ09B0276-0400
Function
Source address
0
register
Destination
0
address register
Transfer counter
0
Initial Setting
Operation
Source start
Incremented or
address
decremented once per
transfer, or held fixed
Destination start
Incremented or
address
decremented once per
transfer, or held fixed
Number of
Decremented once per
transfers
transfer
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