Address Multiplexing; Data Bus - Renesas H8/3067 Series User Manual

6.5.3

Address Multiplexing

When DRAM space is accessed, the row address and column address are multiplexed. The address
multiplexing method is selected with bits MXC1 and MXC0 in DRCRB according to the number
of bits in the DRAM column address. Table 6.6 shows the correspondence between the settings of
MXC1 and MXC0 and the address multiplexing method.
Table 6.6 Settings of Bits MXC1 and MXC0 and Address Multiplexing Method
DRCRB
MXC1 MXC0 Bits
Row 0 0
address
1
1 0
1
Column — —
address
Note: * Row address bit A
6.5.4

Data Bus

If the bit in ABWCR corresponding to an area designated as DRAM space is set to 1, that area is
designated as 8-bit DRAM space; if the bit is cleared to 0, the area is designated as 16-bit DRAM
space. In 16-bit DRAM space, × 16-bit organization DRAM can be connected directly.
In 8-bit DRAM space the upper half of the data bus, D
space both the upper and lower halves of the data bus, D
Access sizes and data alignment are the same as for the basic bus interface: see section 6.4.2, Data
Size and Data Alignment.
Column
Pins
Address Address
A to A A
23 13
8 bits A to A A
23 13
9 bits A to A A
23 13
10 bits A to A A
23 13
Illegal — — — — — — — — — — — — — —
setting
— A to A A
23 13
is not multiplexed in 1-Mbyte mode.
20
A A A A A
12 11 10 9 8 7
* A A A A A
20 19 18 17 16 15
A * A A A A
12 20 19 18 17 16
A A * A A A
12 11 20 19 18 17
A A A A A
12 11 10 9 8 7
to D , is enabled, while in 16-bit DRAM
15 8
to D , are enabled.
15 0
Rev. 4.00 Jan 26, 2006 page 167 of 938
Section 6 Bus Controller
A A A A A A
6 5 4 3 2
A A A A A A
14 13 12 11 10
A A A A A A
15 14 13 12 11
A A A A A A
16 15 14 13 12
A A A A A A
6 5 4 3 2
REJ09B0276-0400
A
1 0
A
9 8
A
10 9
A
11 10
A
1 0