Renesas H8/3067 Series User Manual page 173

CS in the input state. To output chip select signals CS
3
be set to 1. For details, see section 8, I/O Ports.
Output of CS CS to CS CS
CS CS CS CS
4 7
register (CSCR). A reset leaves pins CS
to CS
, the corresponding CSCR bits must be set to 1. For details, see section 8, I/O Ports.
7
Address
CS
When the on-chip ROM, on-chip RAM, and on-chip registers are accessed, CS
high. The CS
signals are decoded from the address signals. They can be used as chip select
n
signals for SRAM and other devices.
: Output of CS to CS
4
to CS
4
φ
n
Figure 6.4 CS CSn Signal Output Timing (n = 0 to 7)
CS CS
to CS
, the corresponding DDR bits must
0 3
is enabled or disabled in the chip select control
7
in the input state. To output chip select signals CS
7
External address in area n
Rev. 4.00 Jan 26, 2006 page 149 of 938
Section 6 Bus Controller
to CS
remain
0 7
REJ09B0276-0400
4