Table of Contents
Advertisement
Pin
Name Mode Reset
PB
1 to 5 T
3
6, 7
T
PB
to
1 to 5 T
5
PB
4
6, 7
T
PB
to
1 to 7 T
7
PB
6
Legend
H:
High
L:
Low
T:
High-impedance state
Keep: Input pins are in the high-impedance state; output pins maintain their previous state.
DDR: Data direction register
Notes: 1. When bits DRAS2, DRAS1, and DRAS0 in DRCRA (DRAM control register A) are all
cleared to 0.
2. When any of bits DRAS2, DRAS1, or DRAS0 in DRCRA (DRAM control register A) is
set to 1.
3. When the setting of bits DRAS2, DRAS1, and DRAS0 in DRCRA (DRAM control
register A) is 010, 100, or 101.
4. When the setting of bits DRAS2, DRAS1, and DRAS0 in DRCRA (DRAM control
register A) is other than 010, 100, 101, or 000.
5. When bit A23E, A22E, or A21E, respectively, in BRCR (bus release control register) is
cleared to 0.
6 When bit A23E, A22E, or A21E, respectively, in BRCR (bus release control register) is
set to 1.
Hardware
Standby
Software Standby
Mode
Mode
RAS4 output *
T
(SSOE=0)
T
(SSOE=1)
H
CS output *
(SSOE=0)
T
(SSOE=1)
H
Otherwise *
Keep
T
Keep
CAS output *
T
(SSOE=0)
T
(SSOE=1)
H
Otherwise *
Keep
T
Keep
T
Keep
Bus-Released
Mode
12
RAS4 output *
T
CS output *
T
Otherwise *
13
Keep
14
—
15
CAS output *
T
Otherwise *
Keep
16
—
Keep
Rev. 4.00 Jan 26, 2006 page 919 of 938
Appendix D Pin States
Program Execution
Mode
12
RAS4 output
RAS4
13
CS output
CS4
14
Otherwise
I/O port
I/O port
15
CAS output
UCAS, LCAS
16
Otherwise
I/O port
I/O port
I/O port
REJ09B0276-0400
Advertisement
Table of Contents
