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Section 7 DMA Controller
Idle mode setup
Set source and
destination addresses
Set transfer count
Read DTCR
Set DTCR
Idle mode
7.4.4
Repeat Mode
Repeat mode is useful for cyclically transferring a bit pattern from a table to the programmable
timing pattern controller (TPC) in synchronization, for example, with 16-bit timer compare match.
Repeat mode can be selected for each channel independently.
One byte or word is transferred per request in repeat mode, as in I/O mode. A designated number
of these transfers are executed. One address is specified in the memory address register (MAR),
the other in the I/O address register (IOAR). At the end of the designated number of transfers,
MAR and ETCRH are restored to their original values and operation continues. The direction of
transfer is determined automatically from the activation source. The transfer is from the address
specified in IOAR to the address specified in MAR if activated by an SCI channel 0 receive-data-
full interrupt, and from the address specified in MAR to the address specified in IOAR otherwise.
Table 7.8 indicates the register functions in repeat mode.
Rev. 4.00 Jan 26, 2006 page 236 of 938
REJ09B0276-0400
1.
Set the source and destination addresses
in MAR and IOAR. The transfer direction is deter-
mined automatically from the activation source.
2.
Set the transfer count in ETCR.
1
3.
Read DTCR while the DTE bit is cleared to 0.
4.
Set the DTCR bits as follows.
•
•
2
•
•
3
4
Figure 7.5 Idle Mode Setup Procedure (Example)
Select the DMAC activation source with bits
DTS2 to DTS0.
Set the DTIE and RPE bits to 1 to select idle mode.
Select byte size or word size with the DTSZ bit.
Set the DTE bit to 1 to enable the transfer.
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