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Section 2 CPU
Reset
Exception
Interrupt
sources
Trap instruction
Bus-released state
End of
exception
handling
Exception-handling state
RES = "High"
Reset state*
Notes: 1.
From any state except hardware standby mode, a transition to the reset state occurs
whenever
2.
From any state, a transition to hardware standby mode occurs when
Rev. 4.00 Jan 26, 2006 page 56 of 938
REJ09B0276-0400
External interrupts
Internal interrupts (from on-chip supporting modules)
Figure 2.12 Classification of Exception Sources
Bus request
End of bus release
Program execution state
End of bus
release
Bus
request
Exception
handling source
Interrupt source
NMI, IRQ , IRQ ,
or IRQ interrupt
2
STBY="High", RES ="Low"
1
RES
goes low.
Figure 2.13 State Transitions
SLEEP
instruction
with SSBY = 0
SLEEP instruction
with SSBY = 1
0
1
Software standby mode
Hardware standby mode*
Sleep mode
2
Power-down state
STBY
goes low.
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