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The receive margin in asynchronous mode can therefore be expressed as shown in equation (1).
(0.5 −
M =
M:
Receive margin (%)
N:
Ratio of clock frequency to bit rate (N = 16)
D:
Clock duty cycle (L = 0 to 1.0)
L:
Frame length (L = 9 to 12)
F:
Absolute deviation of clock frequency
From equation (1), if F = 0 and D = 0.5, the receive margin is 46.875%, as given by equation (2).
D = 0.5, F = 0
(0.5 −
M =
= 46.875%
This is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%.
Restrictions on Use of DMAC:
• When an external clock source is used for the serial clock, after the DMAC updates TDR,
allow an inversion of at least five system clock (φ) cycles before input of the serial clock to
start transmitting. If the serial clock is input within four states of the TDR update, a
malfunction may occur. (See figure 13.22)
• To have the DMAC read RDR, be sure to select the corresponding SCI receive-data-full
interrupt (RXI) as the activation source with bits DTS2 to DTS0 in DTCR.
1
) − (L − 0.5) F −
2N
1
) × 100%
2 × 16
Section 13 Serial Communication Interface
D − 0.5
(1 + F)
N
. . . . . . . . (1)
. . . . . . . . (2)
Rev. 4.00 Jan 26, 2006 page 537 of 938
× 100%
REJ09B0276-0400
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