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Section 21 Electrical Characteristics
Table 21.16 Timing of On-Chip Supporting Modules
Condition:
T
= –20°C to +75°C (regular specifications), T
a
specifications)
Condition A:
V
= 3.0 to 5.5 V, AV
CC
fmax = 13 MHz
Condition B:
V
= 5.0 V ± 10%, AV
CC
fmax = 20 MHz
Item
Port/
Output data delay time
TPC
Input data setup time
Input data hold time
16-bit
Timer output delay time
timer
Timer input setup time
Timer clock input setup time t
Timer clock
Single edge
pulse width Both edges
8-bit
Timer output delay time
timer
Timer input setup time
Timer clock input setup time t
Timer clock
Single edge
pulse width Both edges
SCI
Input clock
Asynchronous
cycle
Synchronous
Input clock rise time
Input clock fall time
Input clock pulse width
Transmit data delay time
Receive data setup time
(synchronous)
Receive
Clock input
data hold
Clock output
time (syn-
chronous)
Rev. 4.00 Jan 26, 2006 page 730 of 938
REJ09B0276-0400
= 3.0 to 5.5 V, V
CC
REF
= 5.0 V ± 10%, V
CC
Condition
A
Symbol Min
Max
t
—
100
PWD
t
50
—
PRS
t
50
—
PRH
t
—
100
TOCD
t
50
—
TICS
50
—
TCKS
t
1.5
—
TCKWH
t
2.5
—
TCKWL
t
—
100
TOCD
t
50
—
TICS
50
—
TCKS
t
1.5
—
TCKWH
t
2.5
—
TCKWL L
t
4
—
Scyc
6
—
t
1.5
—
SCKr
t
1.5
—
SCKf
t
0.4
0.6
SCKW
t
—
100
TXD
t
100
—
RXS
t
100
—
RXH
0
—
= –40°C to +85°C (wide-range
a
= 3.0 to AV
, V
= AV
CC
SS
= 4.5 to AV
, V
REF
CC
SS
B
Min
Max
Unit
—
50
ns
50
—
ns
50
—
ns
—
50
ns
50
—
ns
50
—
ns
1.5
—
t
cyc
2.5
—
t
cyc
—
50
ns
50
—
ns
50
—
ns
1.5
—
t
cyc
2.5
—
t
cyc
4
—
t
cyc
6
—
t
cyc
1.5
—
t
cyc
1.5
—
t
cyc
0.4
0.6
t
Scyc
—
100
ns
100
—
ns
100
—
ns
0
—
ns
= 0 V,
SS
= AV
= 0 V,
SS
Test
Conditions
Figure 21.20
Figure 21.21
Figure 21.22
Figure 21.21
Figure 21.22
Figure 21.23
Figure 21.24
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